3 * Universal Host Controller Interface
14 #define MAX_CONTROLLERS 4
18 int UHCI_Initialise();
20 tUHCI_TD *UHCI_int_AllocateTD(tUHCI_Controller *Cont);
21 void UHCI_int_AppendTD(tUHCI_Controller *Cont, tUHCI_TD *TD);
22 void *UHCI_int_SendTransaction(tUHCI_Controller *Cont, int Addr, Uint8 Type, int bTgl, int bIOC, void *Data, size_t Length);
23 void *UHCI_DataIN(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length);
24 void *UHCI_DataOUT(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length);
25 void *UHCI_SendSetup(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length);
26 int UHCI_Int_InitHost(tUHCI_Controller *Host);
27 void UHCI_InterruptHandler(int IRQ, void *Ptr);
30 tUHCI_TD gaUHCI_TDPool[NUM_TDs];
31 tUHCI_Controller gUHCI_Controllers[MAX_CONTROLLERS];
32 tUSBHost gUHCI_HostDef = {
33 .SendIN = UHCI_DataIN,
34 .SendOUT = UHCI_DataOUT,
35 .SendSETUP = UHCI_SendSetup,
40 * \fn int UHCI_Initialise()
41 * \brief Called to initialise the UHCI Driver
43 int UHCI_Initialise(const char **Arguments)
50 // Enumerate PCI Bus, getting a maximum of `MAX_CONTROLLERS` devices
51 while( (id = PCI_GetDeviceByClass(0x0C03, 0xFFFF, id)) >= 0 && i < MAX_CONTROLLERS )
53 tUHCI_Controller *cinfo = &gUHCI_Controllers[i];
54 // NOTE: Check "protocol" from PCI?
57 // Assign a port range (BAR4, Reserve 32 ports)
58 cinfo->IOBase = PCI_GetBAR(id, 4);
59 if( !(cinfo->IOBase & 1) ) {
60 Log_Warning("UHCI", "MMIO is not supported");
63 cinfo->IRQNum = PCI_GetIRQ(id);
65 Log_Debug("UHCI", "Controller PCI #%i: IO Base = 0x%x, IRQ %i",
66 id, cinfo->IOBase, cinfo->IRQNum);
68 IRQ_AddHandler(cinfo->IRQNum, UHCI_InterruptHandler, cinfo);
71 ret = UHCI_Int_InitHost(&gUHCI_Controllers[i]);
78 USB_RegisterHost(&gUHCI_HostDef, cinfo);
82 if(i == MAX_CONTROLLERS) {
83 Log_Warning("UHCI", "Over "EXPAND_STR(MAX_CONTROLLERS)" UHCI controllers detected, ignoring rest");
85 LEAVE('i', MODULE_ERR_OK);
90 * \fn void UHCI_Cleanup()
91 * \brief Called just before module is unloaded
97 tUHCI_TD *UHCI_int_AllocateTD(tUHCI_Controller *Cont)
100 for(i = 0; i < NUM_TDs; i ++)
102 if(gaUHCI_TDPool[i].Link == 0) {
103 gaUHCI_TDPool[i].Link = 1;
104 return &gaUHCI_TDPool[i];
110 void UHCI_int_AppendTD(tUHCI_Controller *Cont, tUHCI_TD *TD)
112 Log_Warning("UHCI", "TODO: Implement AppendTD");
116 * \brief Send a transaction to the USB bus
117 * \param Cont Controller pointer
118 * \param Addr Function Address * 16 + Endpoint
119 * \param bTgl Data toggle value
121 void *UHCI_int_SendTransaction(tUHCI_Controller *Cont, int Addr, Uint8 Type, int bTgl, int bIOC, void *Data, size_t Length)
125 if( Length > 0x400 ) return NULL; // Controller allows up to 0x500, but USB doesn't
127 td = UHCI_int_AllocateTD(Cont);
130 td->Control = (Length - 1) & 0x7FF;
131 td->Token = ((Length - 1) & 0x7FF) << 21;
132 td->Token |= (bTgl & 1) << 19;
133 td->Token |= (Addr & 0xF) << 15;
134 td->Token |= ((Addr/16) & 0xFF) << 8;
137 // TODO: Ensure 32-bit paddr
138 if( ((tVAddr)Data & PAGE_SIZE) + Length > PAGE_SIZE ) {
139 Log_Warning("UHCI", "TODO: Support non single page transfers");
140 // td->BufferPointer =
144 td->BufferPointer = MM_GetPhysAddr( (tVAddr)Data );
151 UHCI_int_AppendTD(Cont, td);
156 void *UHCI_DataIN(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length)
158 return UHCI_int_SendTransaction(Ptr, Fcn*16+Endpt, 0x69, DataTgl, bIOC, Data, Length);
161 void *UHCI_DataOUT(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length)
163 return UHCI_int_SendTransaction(Ptr, Fcn*16+Endpt, 0xE1, DataTgl, bIOC, Data, Length);
166 void *UHCI_SendSetup(void *Ptr, int Fcn, int Endpt, int DataTgl, int bIOC, void *Data, size_t Length)
168 return UHCI_int_SendTransaction(Ptr, Fcn*16+Endpt, 0x2D, DataTgl, bIOC, Data, Length);
171 // === INTERNAL FUNCTIONS ===
173 * \fn int UHCI_Int_InitHost(tUCHI_Controller *Host)
174 * \brief Initialises a UHCI host controller
175 * \param Host Pointer - Host to initialise
177 int UHCI_Int_InitHost(tUHCI_Controller *Host)
179 ENTER("pHost", Host);
181 outw( Host->IOBase + USBCMD, 4 ); // GRESET
183 // TODO: Wait for at least 10ms
184 outw( Host->IOBase + USBCMD, 0 ); // GRESET
186 // Allocate Frame List
187 // - 1 Page, 32-bit address
188 // - 1 page = 1024 4 byte entries
189 Host->FrameList = (void *) MM_AllocDMA(1, 32, &Host->PhysFrameList);
190 if( !Host->FrameList ) {
191 Log_Warning("UHCI", "Unable to allocate frame list, aborting");
195 LOG("Allocated frame list 0x%x (0x%x)", Host->FrameList, Host->PhysFrameList);
196 memsetd( Host->FrameList, 1, 1024 ); // Clear List (Disabling all entries)
198 //! \todo Properly fill frame list
200 // Set frame length to 1 ms
201 outb( Host->IOBase + SOFMOD, 64 );
204 outd( Host->IOBase + FLBASEADD, Host->PhysFrameList );
205 outw( Host->IOBase + FRNUM, 0 );
208 outw( Host->IOBase + USBINTR, 0x000F );
209 PCI_ConfigWrite( Host->PciId, 0xC0, 2, 0x2000 );
211 outw( Host->IOBase + USBCMD, 0x0001 );
217 void UHCI_CheckPortUpdate(tUHCI_Controller *Host)
220 for( int i = 0; i < 2; i ++ )
222 int port = Host->IOBase + PORTSC1 + i*2;
223 // Check for port change
224 if( !(inw(port) & 0x0002) ) continue;
227 // Check if the port is connected
228 if( !(inw(port) & 1) )
230 // TODO: Tell the USB code it's gone?
235 LOG("Port %i has something", i);
236 // Reset port (set bit 9)
237 outw( port, 0x0100 );
238 Time_Delay(50); // 50ms delay
239 outw( port, inw(port) & ~0x0100 );
241 Time_Delay(50); // 50ms delay
242 outw( port, inw(port) & 0x0004 );
247 void UHCI_InterruptHandler(int IRQ, void *Ptr)
249 Log_Debug("UHCI", "UHIC Interrupt");