9 //#ifndef UDI_PHYSIO_VERSION
10 //# error "UDI_PHYSIO_VERSION must be defined"
13 #define UDI_DL_PIO_HANDLE_T 200
14 #define UDI_DL_DMA_CONSTRAINTS_T 201
18 typedef struct udi_dma_handle_s *udi_dma_handle_t;
19 #define UDI_NULL_DMA_HANDLE _NULL_HANDLE
20 typedef uint64_t udi_busaddr64_t; //!< \note Opaque
21 typedef struct udi_scgth_element_32_s udi_scgth_element_32_t;
22 typedef struct udi_scgth_element_64_s udi_scgth_element_64_t;
23 typedef struct udi_scgth_s udi_scgth_t;
24 typedef struct udi_dma_constraints_s *udi_dma_constraints_t;
25 #define UDI_NULL_DMA_CONSTRAINTS _NULL_HANDLE
27 * \name DMA constraints attributes
30 typedef udi_ubit8_t udi_dma_constraints_attr_t;
31 /* DMA Convenience Attribute Codes */
32 #define UDI_DMA_ADDRESSABLE_BITS 100
33 #define UDI_DMA_ALIGNMENT_BITS 101
34 /* DMA Constraints on the Entire Transfer */
35 #define UDI_DMA_DATA_ADDRESSABLE_BITS 110
36 #define UDI_DMA_NO_PARTIAL 111
37 /* DMA Constraints on the Scatter/Gather List */
38 #define UDI_DMA_SCGTH_MAX_ELEMENTS 120
39 #define UDI_DMA_SCGTH_FORMAT 121
40 #define UDI_DMA_SCGTH_ENDIANNESS 122
41 #define UDI_DMA_SCGTH_ADDRESSABLE_BITS 123
42 #define UDI_DMA_SCGTH_MAX_SEGMENTS 124
43 /* DMA Constraints on Scatter/Gather Segments */
44 #define UDI_DMA_SCGTH_ALIGNMENT_BITS 130
45 #define UDI_DMA_SCGTH_MAX_EL_PER_SEG 131
46 #define UDI_DMA_SCGTH_PREFIX_BYTES 132
47 /* DMA Constraints on Scatter/Gather Elements */
48 #define UDI_DMA_ELEMENT_ALIGNMENT_BITS 140
49 #define UDI_DMA_ELEMENT_LENGTH_BITS 141
50 #define UDI_DMA_ELEMENT_GRANULARITY_BITS 142
51 /* DMA Constraints for Special Addressing */
52 #define UDI_DMA_ADDR_FIXED_BITS 150
53 #define UDI_DMA_ADDR_FIXED_TYPE 151
54 #define UDI_DMA_ADDR_FIXED_VALUE_LO 152
55 #define UDI_DMA_ADDR_FIXED_VALUE_HI 153
56 /* DMA Constraints on DMA Access Behavior */
57 #define UDI_DMA_SEQUENTIAL 160
58 #define UDI_DMA_SLOP_IN_BITS 161
59 #define UDI_DMA_SLOP_OUT_BITS 162
60 #define UDI_DMA_SLOP_OUT_EXTRA 163
61 #define UDI_DMA_SLOP_BARRIER_BITS 164
62 /* Values for UDI_DMA_SCGTH_ENDIANNESS */
63 #define UDI_DMA_LITTLE_ENDIAN (1U<<6)
64 #define UDI_DMA_BIG_ENDIAN (1U<<5)
65 /* Values for UDI_DMA_ADDR_FIXED_TYPE */
66 #define UDI_DMA_FIXED_ELEMENT 1
70 // DMA Constraints Management
71 typedef struct udi_dma_constraints_attr_spec_s udi_dma_constraints_attr_spec_t;
72 typedef void udi_dma_constraints_attr_set_call_t(
73 udi_cb_t *gcb, udi_dma_constraints_t new_constraints, udi_status_t status
75 typedef struct udi_dma_limits_s udi_dma_limits_t;
79 // --- DMA Constraints Management ---
80 struct udi_dma_constraints_attr_spec_s
82 udi_dma_constraints_attr_t attr_type;
83 udi_ubit32_t attr_value;
86 struct udi_dma_limits_s
88 udi_size_t max_legal_contig_alloc;
89 udi_size_t max_safe_contig_alloc;
90 udi_size_t cache_line_size;
92 struct udi_scgth_element_32_s
94 udi_ubit32_t block_busaddr;
95 udi_ubit32_t block_length;
97 struct udi_scgth_element_64_s
99 udi_busaddr64_t block_busaddr;
100 udi_ubit32_t block_length;
101 udi_ubit32_t el_reserved;
104 #define UDI_SCGTH_EXT 0x80000000
107 udi_ubit16_t scgth_num_elements;
108 udi_ubit8_t scgth_format;
109 udi_boolean_t scgth_must_swap;
111 udi_scgth_element_32_t *el32p;
112 udi_scgth_element_64_t *el64p;
115 udi_scgth_element_32_t el32;
116 udi_scgth_element_64_t el64;
117 } scgth_first_segment;
119 /* Values for scgth_format */
120 #define UDI_SCGTH_32 (1U<<0)
121 #define UDI_SCGTH_64 (1U<<1)
122 #define UDI_SCGTH_DMA_MAPPED (1U<<6)
123 #define UDI_SCGTH_DRIVER_MAPPED (1U<<7)
128 #include <physio/dma_const.h>
129 #include <physio/dma.h>
130 #include <physio/meta_intr.h>
131 #include <physio/meta_bus.h>
132 #include "physio/pio.h"
134 #include "physio/pci.h"