1 #Makefile for a VHDL FPU based on https://github.com/jop-devel/jop
3 GHDL_FLAGS = --std=93c --ieee=synopsys -fexplicit
4 OBJ = fpupack.o pre_norm_addsub.o addsub_28.o post_norm_addsub.o pre_norm_mul.o mul_24.o serial_mul.o post_norm_mul.o pre_norm_div.o serial_div.o post_norm_div.o pre_norm_sqrt.o sqrt.o post_norm_sqrt.o comppack.o fpu.o txt_util.o
14 $(GHDL) -e $(GHDL_FLAGS) $@
18 $(GHDL) -a $(GHDL_FLAGS) $<