1 -------------------------------------------------------------------------------
3 -- Project: <Floating Point Unit Core>
5 -- Description: addition/subtraction entity for the addition/subtraction unit
6 -------------------------------------------------------------------------------
8 -- 100101011010011100100
9 -- 110000111011100100000
10 -- 100000111011000101101
11 -- 100010111100101111001
12 -- 110000111011101101001
13 -- 010000001011101001010
14 -- 110100111001001100001
15 -- 110111010000001100111
16 -- 110110111110001011101
17 -- 101110110010111101000
18 -- 100000010111000000000
20 -- Author: Jidan Al-eryani
25 -- This source file may be used and distributed without
26 -- restriction provided that this copyright statement is not
27 -- removed from the file and that any derivative work contains
28 -- the original copyright notice and the associated disclaimer.
30 -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
34 -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
37 -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
39 -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
41 -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 -- POSSIBILITY OF SUCH DAMAGE.
46 use ieee.std_logic_1164.all;
47 use ieee.std_logic_unsigned.all;
48 use ieee.std_logic_misc.all;
49 use IEEE.std_logic_arith.all;
57 fpu_op_i : in std_logic;
58 fracta_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
59 fractb_i : in std_logic_vector(FRAC_WIDTH+4 downto 0);
60 signa_i : in std_logic;
61 signb_i : in std_logic;
62 fract_o : out std_logic_vector(FRAC_WIDTH+4 downto 0);
63 sign_o : out std_logic);
67 architecture rtl of addsub_28 is
69 signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
70 signal s_fract_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
71 signal s_signa_i, s_signb_i, s_sign_o : std_logic;
72 signal s_fpu_op_i : std_logic;
74 signal fracta_lt_fractb : std_logic;
75 signal s_addop: std_logic;
82 -- if rising_edge(clk_i) then
83 s_fracta_i <= fracta_i;
84 s_fractb_i <= fractb_i;
87 s_fpu_op_i <= fpu_op_i;
94 if rising_edge(clk_i) then
100 fracta_lt_fractb <= '1' when s_fracta_i > s_fractb_i else '0';
102 -- check if its a subtraction or an addition operation
103 s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));
106 s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
107 ((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
108 ((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));
111 process(s_fracta_i, s_fractb_i, s_addop, fracta_lt_fractb)
114 s_fract_o <= s_fracta_i + s_fractb_i;
116 if fracta_lt_fractb = '1' then
117 s_fract_o <= s_fracta_i - s_fractb_i;
119 s_fract_o <= s_fractb_i - s_fracta_i;