1 -- Simulates the fpu by reading signals from stdin and writing results to stdout
2 -- See COPYRIGHT.jop for the original copyright notice.
5 use ieee.std_logic_1164.all;
6 use ieee.std_logic_unsigned.all;
7 use ieee.math_real.all;
8 use ieee.std_logic_arith.all;
9 use ieee.std_logic_misc.all;
11 use work.txt_util.all;
15 -- fpu operations (fpu_op_i):
16 -- ========================
28 -- 00 = round to nearest even(default),
29 -- 01 = round to zero,
37 architecture rtl of main is
42 opa_i : in std_logic_vector(31 downto 0);
43 opb_i : in std_logic_vector(31 downto 0);
44 fpu_op_i : in std_logic_vector(2 downto 0);
45 rmode_i : in std_logic_vector(1 downto 0);
46 output_o : out std_logic_vector(31 downto 0);
47 ine_o : out std_logic;
48 overflow_o : out std_logic;
49 underflow_o : out std_logic;
50 div_zero_o : out std_logic;
51 inf_o : out std_logic;
52 zero_o : out std_logic;
53 qnan_o : out std_logic;
54 snan_o : out std_logic;
55 start_i : in std_logic;
56 ready_o : out std_logic
60 -- Assigning default values doesn't seem to help the error messages :(
61 signal clk_i : std_logic:= '1';
62 signal opa_i, opb_i : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
63 signal fpu_op_i : std_logic_vector(2 downto 0) := (others => '0');
64 signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
65 signal output_o : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
66 signal start_i : std_logic := '1';
67 signal ready_o : std_logic := '1';
68 signal ine_o : std_logic := '0';
69 signal overflow_o : std_logic := '0';
70 signal underflow_o : std_logic := '0';
71 signal div_zero_o : std_logic := '0';
72 signal inf_o : std_logic := '0';
73 signal zero_o : std_logic := '0';
74 signal qnan_o : std_logic := '0';
75 signal snan_o : std_logic := '0';
79 signal slv_out : std_logic_vector(FP_WIDTH-1 downto 0);
81 constant CLK_PERIOD :time := 10 ns; -- period of clk period
95 overflow_o => overflow_o,
96 underflow_o => underflow_o,
97 div_zero_o => div_zero_o,
106 ---------------------------------------------------------------------------
108 ---------------------------------------------------------------------------
109 clk_i <= not(clk_i) after 5 ns;
113 --The operands and results are in Hex format.
114 file input_file: TEXT open read_mode is "STD_INPUT";
116 variable file_line: line;
117 variable str_in: string(FP_WIDTH/4 downto 1);
118 variable str_fpu_op: string(3 downto 1);
119 variable str_rmode: string(2 downto 1);
124 -- Read ops from input_file
125 --print(str(ZERO_VECTOR));
130 while not endfile(input_file) loop
135 str_read(input,str_in);
136 opa_i <= strhex_to_slv(str_in);
138 str_read(input,str_in);
139 opb_i <= strhex_to_slv(str_in);
141 str_read(input_file,str_fpu_op);
142 fpu_op_i <= to_std_logic_vector(str_fpu_op);
144 str_read(input_file,str_rmode);
145 rmode_i <= to_std_logic_vector(str_rmode);
147 str_read(input_file,str_in);
148 slv_out <= strhex_to_slv(str_in);
152 wait until ready_o='1';
155 print(hstr(output_o));
159 end process mainloop;