1 -- Simulates the fpu by reading signals from stdin and writing results to stdout
2 -- See COPYRIGHT.jop for the original copyright notice.
5 use ieee.std_logic_1164.all;
6 use ieee.std_logic_unsigned.all;
7 use ieee.math_real.all;
8 use ieee.std_logic_arith.all;
9 use ieee.std_logic_misc.all;
11 use work.txt_util.all;
13 -- fpu operations (fpu_op_i):
14 -- ========================
26 -- 00 = round to nearest even(default),
27 -- 01 = round to zero,
35 architecture rtl of main is
40 opa_i : in std_logic_vector(31 downto 0);
41 opb_i : in std_logic_vector(31 downto 0);
42 fpu_op_i : in std_logic_vector(2 downto 0);
43 rmode_i : in std_logic_vector(1 downto 0);
44 output_o : out std_logic_vector(31 downto 0);
45 ine_o : out std_logic;
46 overflow_o : out std_logic;
47 underflow_o : out std_logic;
48 div_zero_o : out std_logic;
49 inf_o : out std_logic;
50 zero_o : out std_logic;
51 qnan_o : out std_logic;
52 snan_o : out std_logic;
53 start_i : in std_logic;
54 ready_o : out std_logic
59 signal clk_i : std_logic:= '1';
60 signal opa_i, opb_i : std_logic_vector(31 downto 0) := (others => '0');
61 signal fpu_op_i : std_logic_vector(2 downto 0) := (others => '0');
62 signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
63 signal output_o : std_logic_vector(31 downto 0) := (others => '0');
64 signal start_i, ready_o : std_logic := '0';
65 signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
69 signal slv_out : std_logic_vector(31 downto 0);
71 constant CLK_PERIOD :time := 10 ns; -- period of clk period
85 overflow_o => overflow_o,
86 underflow_o => underflow_o,
87 div_zero_o => div_zero_o,
96 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 clk_i <= not(clk_i) after 5 ns;
103 --The operands and results are in Hex format.
104 file input_file: TEXT open read_mode is "STD_INPUT";
106 variable file_line: line;
107 variable str_in: string(8 downto 1);
108 variable str_fpu_op: string(3 downto 1);
109 variable str_rmode: string(2 downto 1);
114 -- Read ops from input_file
116 while not endfile(input_file) loop
121 str_read(input,str_in);
122 opa_i <= strhex_to_slv(str_in);
124 str_read(input,str_in);
125 opb_i <= strhex_to_slv(str_in);
127 str_read(input_file,str_fpu_op);
128 fpu_op_i <= to_std_logic_vector(str_fpu_op);
130 str_read(input_file,str_rmode);
131 rmode_i <= to_std_logic_vector(str_rmode);
133 str_read(input_file,str_in);
134 slv_out <= strhex_to_slv(str_in);
138 wait until ready_o='1';
141 print(hstr(output_o));
145 end process mainloop;