1 -------------------------------------------------------------------------------
3 -- Project: <Floating Point Unit Core>
5 -- Description: post-normalization entity for the addition/subtraction unit
6 -------------------------------------------------------------------------------
8 -- 100101011010011100100
9 -- 110000111011100100000
10 -- 100000111011000101101
11 -- 100010111100101111001
12 -- 110000111011101101001
13 -- 010000001011101001010
14 -- 110100111001001100001
15 -- 110111010000001100111
16 -- 110110111110001011101
17 -- 101110110010111101000
18 -- 100000010111000000000
20 -- Author: Jidan Al-eryani
25 -- This source file may be used and distributed without
26 -- restriction provided that this copyright statement is not
27 -- removed from the file and that any derivative work contains
28 -- the original copyright notice and the associated disclaimer.
30 -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
34 -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
37 -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
39 -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
41 -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 -- POSSIBILITY OF SUCH DAMAGE.
46 use ieee.std_logic_1164.all;
47 use ieee.std_logic_unsigned.all;
48 use ieee.std_logic_misc.all;
53 entity post_norm_addsub is
56 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
57 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
58 fract_28_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
59 exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
60 sign_i : in std_logic;
61 fpu_op_i : in std_logic;
62 rmode_i : in std_logic_vector(1 downto 0);
63 output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
69 architecture rtl of post_norm_addsub is
72 signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
73 signal s_fract_28_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
74 signal s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
75 signal s_sign_i : std_logic;
76 signal s_fpu_op_i : std_logic;
77 signal s_rmode_i : std_logic_vector(1 downto 0);
78 signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
79 signal s_ine_o : std_logic;
80 signal s_overflow : std_logic;
82 signal s_zeros, s_shr1, s_shl1 : std_logic_vector(5 downto 0);
83 signal s_shr2, s_carry : std_logic;
85 signal s_exp10: std_logic_vector(9 downto 0);
86 signal s_expo9_1, s_expo9_2, s_expo9_3: std_logic_vector(EXP_WIDTH downto 0);
88 signal s_fracto28_1, s_fracto28_2, s_fracto28_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0);
90 signal s_roundup : std_logic;
91 signal s_sticky : std_logic;
93 signal s_zero_fract : std_logic;
94 signal s_lost : std_logic;
95 signal s_infa, s_infb : std_logic;
96 signal s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign : std_logic;
103 -- if rising_edge(clk_i) then
106 s_fract_28_i <= fract_28_i;
109 s_fpu_op_i <= fpu_op_i;
110 s_rmode_i <= rmode_i;
117 if rising_edge(clk_i) then
118 output_o <= s_output_o;
124 -- figure out the output exponent and howmuch the fraction has to be shiftd right/left
126 s_carry <= s_fract_28_i(27);
129 s_zeros <= count_l_zeros(s_fract_28_i(26 downto 0)) when s_fract_28_i(27)='0' else "000000";
132 s_exp10 <= ("00"&s_exp_i) + ("000000000"&s_carry) - ("0000"&s_zeros); -- negative flag & large flag & exp
136 if rising_edge(clk_i) then
137 if s_exp10(9)='1' or s_exp10="0000000000" then
138 s_shr1 <= (others =>'0');
139 if or_reduce(s_exp_i)/='0' then
140 s_shl1 <= s_exp_i(5 downto 0) - "000001";
144 s_expo9_1 <= "000000001";
145 elsif s_exp10(8)='1' then
146 s_shr1 <= (others =>'0');
147 s_shl1 <= (others =>'0');
148 s_expo9_1 <= "011111111";
150 s_shr1 <= ("00000"&s_carry);
152 s_expo9_1 <= s_exp10(8 downto 0);
159 -- Shifting the fraction and rounding
163 if rising_edge(clk_i) then
164 if s_shr1 /= "000000" then
165 s_fracto28_1 <= shr(s_fract_28_i, s_shr1);
167 s_fracto28_1 <= shl(s_fract_28_i, s_shl1);
172 s_expo9_2 <= s_expo9_1 - "000000001" when s_fracto28_1(27 downto 26)="00" else s_expo9_1;
175 s_sticky <='1' when s_fracto28_1(0)='1' or (s_fract_28_i(0) and s_fract_28_i(27))='1' else '0'; --check last bit, before and after right-shift
177 s_roundup <= s_fracto28_1(2) and ((s_fracto28_1(1) or s_sticky)or s_fracto28_1(3)) when s_rmode_i="00" else -- round to nearset even
178 (s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
179 (s_fracto28_1(2) or s_fracto28_1(1) or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
180 '0'; -- round to zero(truncate = no rounding)
182 s_fracto28_rnd <= s_fracto28_1 + "0000000000000000000000001000" when s_roundup='1' else s_fracto28_1;
185 -- right-shift after rounding (if necessary)
186 s_shr2 <= s_fracto28_rnd(27);
188 s_expo9_3 <= s_expo9_2 + "000000001" when s_shr2='1' and s_expo9_2 /= "011111111" else s_expo9_2;
189 s_fracto28_2 <= ("0"&s_fracto28_rnd(27 downto 1)) when s_shr2='1' else s_fracto28_rnd;
192 s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
193 s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
195 s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
196 s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
197 s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0';
198 s_nan_op <= '1' when (s_infa and s_infb)='1' and (s_opa_i(31) xor (s_fpu_op_i xor s_opb_i(31)) )='1' else '0'; -- inf-inf=Nan
200 s_nan_sign <= s_sign_i when (s_nan_a and s_nan_b)='1' else
201 s_opa_i(31) when s_nan_a='1' else
204 -- check if result is inexact;
205 s_lost <= (s_shr1(0) and s_fract_28_i(0)) or (s_shr2 and s_fracto28_rnd(0)) or or_reduce(s_fracto28_2(2 downto 0));
206 s_ine_o <= '1' when (s_lost or s_overflow)='1' and (s_infa or s_infb)='0' else '0';
208 s_overflow <='1' when s_expo9_3="011111111" and (s_infa or s_infb)='0' else '0';
209 s_zero_fract <= '1' when s_zeros=27 and s_fract_28_i(27)='0' else '0'; -- '1' if fraction result is zero
211 process(s_sign_i, s_expo9_3, s_fracto28_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow, s_zero_fract)
213 if (s_nan_in or s_nan_op)='1' then
214 s_output_o <= s_nan_sign & QNAN;
215 elsif (s_infa or s_infb)='1' or s_overflow='1' then
216 s_output_o <= s_sign_i & INF;
217 elsif s_zero_fract='1' then
218 s_output_o <= s_sign_i & ZERO_VECTOR;
220 s_output_o <= s_sign_i & s_expo9_3(7 downto 0) & s_fracto28_2(25 downto 3);