1 -------------------------------------------------------------------------------
3 -- Project: <Floating Point Unit Core>
5 -- Description: pre-normalization entity for the division unit
6 -------------------------------------------------------------------------------
8 -- 100101011010011100100
9 -- 110000111011100100000
10 -- 100000111011000101101
11 -- 100010111100101111001
12 -- 110000111011101101001
13 -- 010000001011101001010
14 -- 110100111001001100001
15 -- 110111010000001100111
16 -- 110110111110001011101
17 -- 101110110010111101000
18 -- 100000010111000000000
20 -- Author: Jidan Al-eryani
25 -- This source file may be used and distributed without
26 -- restriction provided that this copyright statement is not
27 -- removed from the file and that any derivative work contains
28 -- the original copyright notice and the associated disclaimer.
30 -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
34 -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
37 -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
39 -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
41 -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 -- POSSIBILITY OF SUCH DAMAGE.
46 use ieee.std_logic_1164.all;
47 use ieee.std_logic_unsigned.all;
48 use ieee.std_logic_misc.all;
53 entity pre_norm_div is
56 opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
57 opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
58 exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);
59 dvdnd_50_o : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
60 dvsor_27_o : out std_logic_vector(FRAC_WIDTH+3 downto 0)
64 architecture rtl of pre_norm_div is
67 signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
68 signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
69 signal s_dvdnd_50_o : std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
70 signal s_dvsor_27_o : std_logic_vector(FRAC_WIDTH+3 downto 0);
71 signal s_dvd_zeros, s_div_zeros: std_logic_vector(5 downto 0);
72 signal s_exp_10_o : std_logic_vector(EXP_WIDTH+1 downto 0);
74 signal s_expa_in, s_expb_in : std_logic_vector(EXP_WIDTH+1 downto 0);
75 signal s_opa_dn, s_opb_dn : std_logic;
76 signal s_fracta_24, s_fractb_24 : std_logic_vector(FRAC_WIDTH downto 0);
80 s_expa <= opa_i(30 downto 23);
81 s_expb <= opb_i(30 downto 23);
82 s_fracta <= opa_i(22 downto 0);
83 s_fractb <= opb_i(22 downto 0);
84 dvdnd_50_o <= s_dvdnd_50_o;
85 dvsor_27_o <= s_dvsor_27_o;
90 if rising_edge(clk_i) then
91 exp_10_o <= s_exp_10_o;
96 s_opa_dn <= not or_reduce(s_expa);
97 s_opb_dn <= not or_reduce(s_expb);
99 s_fracta_24 <= (not s_opa_dn) & s_fracta;
100 s_fractb_24 <= (not s_opb_dn) & s_fractb;
102 -- count leading zeros
103 s_dvd_zeros <= count_l_zeros( s_fracta_24 );
104 s_div_zeros <= count_l_zeros( s_fractb_24 );
106 -- left-shift the dividend and divisor
107 s_dvdnd_50_o <= shl(s_fracta_24, s_dvd_zeros) & "00000000000000000000000000";
108 s_dvsor_27_o <= "000" & shl(s_fractb_24, s_div_zeros);
114 if rising_edge(clk_i) then
115 -- pre-calculate exponent
116 s_expa_in <= ("00"&s_expa) + ("000000000"&s_opa_dn);
117 s_expb_in <= ("00"&s_expb) + ("000000000"&s_opb_dn);
118 s_exp_10_o <= s_expa_in - s_expb_in + "0001111111" -("0000"&s_dvd_zeros) + ("0000"&s_div_zeros);