* e1000.c
* - Intel 8254x Network Card Driver (core)
*/
-#define DEBUG 1
+#define DEBUG 0
#define VERSION VER2(0,1)
#include <acess.h>
#include "e1000.h"
// Allocate card array
gaE1000_Cards = calloc(sizeof(tCard), card_count);
if( !gaE1000_Cards ) {
+ Log_Warning("E1000", "Allocation of %i card structures failed", card_count);
return MODULE_ERR_MALLOC;
}
for( int id = -1, i = 0; (id = PCI_GetDevice(cardtype->Vendor, cardtype->Device, i)) != -1; i ++ )
{
tCard *card = &gaE1000_Cards[card_idx++];
- Uint32 mmiobase = PCI_GetBAR(id, 0);
- if( mmiobase & (1|8) ) {
+ card->MMIOBasePhys = PCI_GetValidBAR(id, 0, PCI_BARTYPE_MEMNP);
+ if( !card->MMIOBasePhys ) {
Log_Warning("E1000", "Dev %i: BAR0 should be non-prefetchable memory", id);
continue;
}
- const int addrsize = (mmiobase>>1) & 3;
- if( addrsize == 0 ) {
- // Standard 32-bit
- card->MMIOBasePhys = mmiobase & ~0xF;
- }
- else if( addrsize == 2 ) {
- // 64-bit
- card->MMIOBasePhys = (mmiobase & ~0xF) | ((Uint64)PCI_GetBAR(id, 1)<<32);
- }
- else {
- Log_Warning("E1000", "Dev %i: Unknown memory address size %i", id, (mmiobase>>1)&3);
- continue;
- }
card->IRQ = PCI_GetIRQ(id);
IRQ_AddHandler(card->IRQ, E1000_IRQHandler, card);
-
+ PCI_SetCommand(id, PCI_CMD_MEMENABLE|PCI_CMD_BUSMASTER, 0);
+
Log_Debug("E1000", "Card %i: %P IRQ %i", card_idx, card->MMIOBasePhys, card->IRQ);
if( E1000_int_InitialiseCard(card) ) {
+ Log_Warning("E1000", "Initialisation of card #%i failed", card_idx);
return MODULE_ERR_MALLOC;
}
{
tCard **cardptr = Arg;
tCard *Card = *cardptr;
- int rxd = (Arg - (void*)Card->RXDescs) / sizeof(tRXDesc);
-
+ int rxd = (Arg - (void*)Card->RXBackHandles) / sizeof(void*);
+
+ LOG("RXD %p %i being released", Card, rxd);
+ ASSERT(rxd >= 0 && rxd < NUM_RX_DESC);
+
Card->RXDescs[rxd].Status = 0;
Mutex_Acquire(&Card->lRXDescs);
if( rxd == REG32(Card, REG_RDT) ) {
int txd = first_txd;
while( (idx = IPStack_Buffer_GetBuffer(Buffer, idx, &len, &ptr)) != -1 )
{
+ //Debug_HexDump("E100 SendPacket", ptr, len);
if( MM_GetPhysAddr(ptr) + len-1 != MM_GetPhysAddr((char*)ptr + len-1) )
{
size_t remlen = PAGE_SIZE - ((tVAddr)ptr & (PAGE_SIZE-1));
else
{
// Single
- Card->TXDescs[txd].Buffer = MM_GetPhysAddr(ptr);
- Card->TXDescs[txd].Length = len;
- Card->TXDescs[txd].CMD = TXD_CMD_RS;
+ volatile tTXDesc *txdp = &Card->TXDescs[txd];
+ txdp->Buffer = MM_GetPhysAddr(ptr);
+ txdp->Length = len;
+ txdp->CMD = TXD_CMD_RS;
+ LOG("%P: %llx %x %x", MM_GetPhysAddr((void*)txdp), txdp->Buffer, txdp->Length, txdp->CMD);
}
txd = (txd + 1) % NUM_TX_DESC;
}
Card->TXDescs[last_txd].CMD |= TXD_CMD_EOP|TXD_CMD_IDE|TXD_CMD_IFCS;
Card->TXSrcBuffers[last_txd] = Buffer;
+ __sync_synchronize();
+ #if DEBUG
+ {
+ volatile tTXDesc *txdp = Card->TXDescs + last_txd;
+ LOG("%p %P: %llx %x %x", txdp, MM_GetPhysAddr((void*)txdp), txdp->Buffer, txdp->Length, txdp->CMD);
+ volatile tTXDesc *txdp_base = MM_MapTemp(MM_GetPhysAddr((void*)Card->TXDescs));
+ txdp = txdp_base + last_txd;
+ LOG("%p %P: %llx %x %x", txdp, MM_GetPhysAddr((void*)txdp), txdp->Buffer, txdp->Length, txdp->CMD);
+ MM_FreeTemp( (void*)txdp_base);
+ }
+ #endif
// Trigger TX
IPStack_Buffer_LockBuffer(Buffer);
+ LOG("Triggering TX - Buffers[%i]=%p", last_txd, Buffer);
REG32(Card, REG_TDT) = Card->FirstFreeTXD;
Mutex_Release(&Card->lTXDescs);
- LOG("Waiting for TX");
+ LOG("Waiting for TX to complete");
// Wait for completion (lock will block, then release straight away)
IPStack_Buffer_LockBuffer(Buffer);
if( (icr & ICR_TXDW) || (icr & ICR_TXQE) )
{
int nReleased = 0;
+ int txd = Card->LastFreeTXD;
+ int nReleasedAtLastDD = 0;
+ int idxOfLastDD = txd;
// Walk descriptors looking for the first non-complete descriptor
LOG("TX %i:%i", Card->LastFreeTXD, Card->FirstFreeTXD);
- while( Card->LastFreeTXD != Card->FirstFreeTXD && (Card->TXDescs[Card->LastFreeTXD].Status & TXD_STS_DD) )
+ while( txd != Card->FirstFreeTXD )
{
nReleased ++;
- if( Card->TXSrcBuffers[Card->LastFreeTXD] ) {
- IPStack_Buffer_UnlockBuffer( Card->TXSrcBuffers[Card->LastFreeTXD] );
- Card->TXSrcBuffers[Card->LastFreeTXD] = NULL;
+ if(Card->TXDescs[txd].Status & TXD_STS_DD) {
+ nReleasedAtLastDD = nReleased;
+ idxOfLastDD = txd;
}
- Card->LastFreeTXD ++;
- if(Card->LastFreeTXD == NUM_TX_DESC)
- Card->LastFreeTXD = 0;
+ txd ++;
+ if(txd == NUM_TX_DESC)
+ txd = 0;
}
- Semaphore_Signal(&Card->FreeTxDescs, nReleased);
- LOG("nReleased = %i", nReleased);
- }
-
+ if( nReleasedAtLastDD )
+ {
+ // Unlock buffers
+ txd = Card->LastFreeTXD;
+ LOG("TX unlocking range %i-%i", txd, idxOfLastDD);
+ while( txd != (idxOfLastDD+1)%NUM_TX_DESC )
+ {
+ if( Card->TXSrcBuffers[txd] ) {
+ LOG("- Unlocking %i:%p", txd, Card->TXSrcBuffers[txd]);
+ IPStack_Buffer_UnlockBuffer( Card->TXSrcBuffers[txd] );
+ Card->TXSrcBuffers[txd] = NULL;
+ }
+ txd ++;
+ if(txd == NUM_TX_DESC)
+ txd = 0;
+ }
+ // Update last free
+ Card->LastFreeTXD = txd;
+ Semaphore_Signal(&Card->FreeTxDescs, nReleasedAtLastDD);
+ LOG("nReleased = %i", nReleasedAtLastDD);
+ }
+ else
+ {
+ LOG("No completed TXDs");
+ }
+ }
+
if( icr & ICR_LSC )
{
// Link status change
LOG("LSC");
// TODO: Detect link drop/raise and poke IPStack
}
+
+ if( icr & ICR_RXO )
+ {
+ LOG("RX Overrun");
+ }
// Pending packet (s)
if( icr & ICR_RXT0 )
LOG("nPackets = %i", nPackets);
}
- icr &= ~(ICR_RXT0|ICR_LSC|ICR_TXQE|ICR_TXDW);
+ // Transmit Descriptor Low Threshold hit
+ if( icr & ICR_TXD_LOW )
+ {
+
+ }
+
+ // Receive Descriptor Minimum Threshold Reached
+ // - We're reading too slow
+ if( icr & ICR_RXDMT0 )
+ {
+ LOG("RX descs running out");
+ }
+
+ icr &= ~(ICR_RXT0|ICR_LSC|ICR_TXQE|ICR_TXDW|ICR_TXD_LOW|ICR_RXDMT0);
if( icr )
Log_Warning("E1000", "Unhandled ICR bits 0x%x", icr);
}
size_t ofs = 0;
const int bufs_per_page = PAGE_SIZE / BufSize;
ASSERT(bufs_per_page * BufSize == PAGE_SIZE);
- void *page;
+ void *page = NULL;
for( int i = 0; i < NumBufs; i ++ )
{
if( ofs == 0 ) {
LEAVE('i', 4);
return 4;
}
+ LOG("Card->RXDescs = %p [%P]", Card->TXDescs, MM_GetPhysAddr((void*)Card->TXDescs));
for( int i = 0; i < NUM_TX_DESC; i ++ )
{
Card->TXDescs[i].Buffer = 0;