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Kernel/armv7 - Debugging, fixed TLB issues with a HACK!
[tpg/acess2.git]
/
Kernel
/
arch
/
armv7
/
proc.S
diff --git
a/Kernel/arch/armv7/proc.S
b/Kernel/arch/armv7/proc.S
index
4d7c89f
..
531de29
100644
(file)
--- a/
Kernel/arch/armv7/proc.S
+++ b/
Kernel/arch/armv7/proc.S
@@
-47,7
+47,7
@@
SwitchTask:
tst r1, r1
mcrne p15, 0, r1, c2, c0, 0 @ Set TTBR0 to r0
mov r1, #0
tst r1, r1
mcrne p15, 0, r1, c2, c0, 0 @ Set TTBR0 to r0
mov r1, #0
- mcrne p15, 0, r1, c8, c7, 0 @
Invalidate all (HACK! But it fixes things)
+ mcrne p15, 0, r1, c8, c7, 0 @
TLBIALL - Invalidate all
@ Restore SP
mov sp, r0
@ Restore SP
mov sp, r0
@@
-99,4
+99,6
@@
Proc_int_DropToUser:
.section .rodata
csProc_CloneInt_NewTaskMessage:
.section .rodata
csProc_CloneInt_NewTaskMessage:
- .asciz "New task"
+ .asciz "New task PC=%p, R4=%p, sp=%p"
+csProc_CloneInt_OldTaskMessage:
+ .asciz "Parent task PC=%p, R4=%p, SP=%p"
UCC
git Repository :: git.ucc.asn.au