+void pci_intr_ch_event_ind(udi_channel_event_cb_t *cb)
+{
+ UNIMPLEMENTED();
+}
+void pci_intr_event_rdy(udi_intr_event_cb_t *cb)
+{
+ pci_child_chan_context_t *context = UDI_GCB(cb)->context;
+
+ ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
+ ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
+
+ LOG("Rd %i, Wr %i [WR %p{%p}]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb, cb->event_buf);
+ if( context->event_cbs[context->event_cb_wr_ofs] )
+ {
+ // oops, overrun.
+ return ;
+ }
+ context->event_cbs[context->event_cb_wr_ofs++] = cb;
+ if( context->event_cb_wr_ofs == PCI_MAX_EVENT_CBS )
+ context->event_cb_wr_ofs = 0;
+
+ // TODO: Fire once >= min_event_pend CBs are recieved
+ if( !context->bIntrEnabled )
+ {
+ context->bIntrEnabled = 1;
+ udi_pio_trans(pci_intr_event_rdy__irqs_enabled, NULL, context->intr_preprocessing, 0, NULL, NULL);
+ }
+}
+void pci_intr_event_rdy__irqs_enabled(udi_cb_t *gcb, udi_buf_t *newbuf, udi_status_t status, udi_ubit16_t result)
+{
+ // Do nothing
+}
+
+void pci_intr_handler(int irq, void *void_context)
+{
+ pci_child_chan_context_t *context = void_context;
+
+ LOG("irq=%i, context=%p", irq, context);
+
+ if( context->event_cb_rd_ofs == context->event_cb_wr_ofs ) {
+ // Dropped
+ return ;
+ }
+
+ ASSERTC(context->event_cb_rd_ofs, <, PCI_MAX_EVENT_CBS);
+ ASSERTC(context->event_cb_wr_ofs, <, PCI_MAX_EVENT_CBS);
+
+ udi_intr_event_cb_t *cb = context->event_cbs[context->event_cb_rd_ofs];
+ LOG("Rd %i, Wr %i [RD %p]", context->event_cb_rd_ofs, context->event_cb_wr_ofs, cb);
+ context->event_cbs[context->event_cb_rd_ofs] = NULL;
+ context->event_cb_rd_ofs ++;
+ if( context->event_cb_rd_ofs == PCI_MAX_EVENT_CBS )
+ context->event_cb_rd_ofs = 0;
+ ASSERT(cb);
+ ASSERT(cb->gcb.scratch);
+
+ if( UDI_HANDLE_IS_NULL(context->intr_preprocessing, udi_pio_handle_t) )
+ {
+ // TODO: Ensure region is an interrupt region
+ udi_intr_event_ind(cb, 0);
+ }
+ else
+ {
+ // Processing
+ *(udi_ubit8_t*)(cb->gcb.scratch) = 0;
+ // - no event info, so mem_ptr=NULL
+ udi_pio_trans(pci_intr_handle__trans_done, UDI_GCB(cb),
+ context->intr_preprocessing, 1, cb->event_buf, NULL);
+ // V V V
+ }
+}
+
+void pci_intr_handle__trans_done(udi_cb_t *gcb, udi_buf_t *new_buf, udi_status_t status, udi_ubit16_t result)
+{
+ udi_intr_event_cb_t *cb = UDI_MCB(gcb, udi_intr_event_cb_t);
+ LOG("cb(%p)->event_buf=%p, new_buf=%p",
+ cb, cb->event_buf, new_buf);
+
+ // TODO: Buffers should not change
+ cb->event_buf = new_buf;
+ cb->intr_result = result;
+
+ udi_ubit8_t intr_status = *(udi_ubit8_t*)(gcb->scratch);
+ if( intr_status & UDI_INTR_UNCLAIMED )
+ {
+ // Not claimed, next please.
+ // NOTE: Same as no event in the acess model
+ LOG("Unclaimed");
+ pci_intr_event_rdy(cb);
+ }
+ else if( intr_status & UDI_INTR_NO_EVENT )
+ {
+ // No event should be generated, return cb to pool
+ // EVIL!
+ pci_intr_event_rdy(cb);
+ LOG("No event, return cb to pool");
+ }
+ else
+ {
+ LOG("Inform driver");
+ udi_intr_event_ind(cb, UDI_INTR_PREPROCESSED);
+ }
+}
+
+// - physio hooks
+udi_status_t pci_pio_do_io(uint32_t child_ID, udi_ubit32_t regset_idx, udi_ubit32_t ofs, udi_ubit8_t len,
+ void *data, bool isOutput)
+{
+// LOG("child_ID=%i, regset_idx=%i,ofs=0x%x,len=%i,data=%p,isOutput=%b",
+// child_ID, regset_idx, ofs, len, data, isOutput);
+ tPCIDev pciid = child_ID;
+ // TODO: Cache child mappings
+
+ switch(regset_idx)
+ {
+ case UDI_PCI_CONFIG_SPACE:
+ // TODO:
+ return UDI_STAT_NOT_SUPPORTED;
+ case UDI_PCI_BAR_0 ... UDI_PCI_BAR_5: {
+ Uint32 bar = PCI_GetBAR(pciid, regset_idx);
+ if(bar & 1)
+ {
+ // IO BAR
+ bar &= ~3;
+ #define _IO(fc, type) do {\
+ if( isOutput ) { \
+ /*LOG("out"#fc"(0x%x, 0x%x)",bar+ofs,*(type*)data);*/\
+ out##fc(bar+ofs, *(type*)data); \
+ } \
+ else { \
+ *(type*)data = in##fc(bar+ofs); \
+ /*LOG("in"#fc"(0x%x) = 0x%x",bar+ofs,*(type*)data);*/\
+ }\
+ } while(0)
+ switch(len)
+ {
+ case UDI_PIO_1BYTE: _IO(b, udi_ubit8_t); return UDI_OK;
+ case UDI_PIO_2BYTE: _IO(w, udi_ubit16_t); return UDI_OK;
+ case UDI_PIO_4BYTE: _IO(d, udi_ubit32_t); return UDI_OK;
+ //case UDI_PIO_8BYTE: _IO(q, uint64_t); return UDI_OK;
+ default:
+ return UDI_STAT_NOT_SUPPORTED;
+ }
+ #undef _IO
+ }
+ else
+ {
+ // Memory BAR
+ //Uint64 longbar = PCI_GetValidBAR(pciid, regset_idx, PCI_BARTYPE_MEM);
+ return UDI_STAT_NOT_SUPPORTED;
+ }
+ break; }
+ default:
+ return UDI_STAT_NOT_UNDERSTOOD;
+ }
+}
+