+// === STRUCTURES ===
+// --- DMA Constraints Management ---
+struct udi_dma_constraints_attr_spec_s
+{
+ udi_dma_constraints_attr_t attr_type;
+ udi_ubit32_t attr_value;
+};
+// --- DMA Core ---
+struct udi_dma_limits_s
+{
+ udi_size_t max_legal_contig_alloc;
+ udi_size_t max_safe_contig_alloc;
+ udi_size_t cache_line_size;
+};
+struct udi_scgth_element_32_s
+{
+ udi_ubit32_t block_busaddr;
+ udi_ubit32_t block_length;
+};
+struct udi_scgth_element_64_s
+{
+ udi_busaddr64_t block_busaddr;
+ udi_ubit32_t block_length;
+ udi_ubit32_t el_reserved;
+};
+/* Extension Flag */
+#define UDI_SCGTH_EXT 0x80000000
+struct udi_scgth_s
+{
+ udi_ubit16_t scgth_num_elements;
+ udi_ubit8_t scgth_format;
+ udi_boolean_t scgth_must_swap;
+ union {
+ udi_scgth_element_32_t *el32p;
+ udi_scgth_element_64_t *el64p;
+ } scgth_elements;
+ union {
+ udi_scgth_element_32_t el32;
+ udi_scgth_element_64_t el64;
+ } scgth_first_segment;
+};
+/* Values for scgth_format */
+#define UDI_SCGTH_32 (1U<<0)
+#define UDI_SCGTH_64 (1U<<1)
+#define UDI_SCGTH_DMA_MAPPED (1U<<6)
+#define UDI_SCGTH_DRIVER_MAPPED (1U<<7)
+
+
+
+// === FUNCTIONS ===
+// --- DMA Constraints Management ---
+extern void udi_dma_constraints_attr_set(
+ udi_dma_constraints_attr_set_call_t *callback,
+ udi_cb_t *gcb,
+ udi_dma_constraints_t src_constraints,
+ const udi_dma_constraints_attr_spec_t *attr_list,
+ udi_ubit16_t list_length,
+ udi_ubit8_t flags
+ );
+/* Constraints Flags */
+#define UDI_DMA_CONSTRAINTS_COPY (1U<<0)
+
+extern void udi_dma_constraints_attr_reset(
+ udi_dma_constraints_t constraints,
+ udi_dma_constraints_attr_t attr_type
+ );
+
+extern void udi_dma_constraints_free(udi_dma_constraints_t constraints);
+
+#include <physio/meta_intr.h>
+#include <physio/meta_bus.h>
+