-signal output_o : std_logic_vector(31 downto 0) := (others => '0');
-signal start_i, ready_o : std_logic := '0';
-signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
+signal output_o : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
+signal start_i : std_logic := '1';
+signal ready_o : std_logic := '1';
+signal ine_o : std_logic := '0';
+signal overflow_o : std_logic := '0';
+signal underflow_o : std_logic := '0';
+signal div_zero_o : std_logic := '0';
+signal inf_o : std_logic := '0';
+signal zero_o : std_logic := '0';
+signal qnan_o : std_logic := '0';
+signal snan_o : std_logic := '0';