Kernel/armv7 - Debugging, fixed TLB issues with a HACK!

[tpg/acess2.git] / Kernel / arch / armv7 / start.S

diff --git a/Kernel/arch/armv7/start.S b/Kernel/arch/armv7/start.S
index da57360..8d9f3e4 100644 (file)
--- a/Kernel/arch/armv7/start.S
+++ b/Kernel/arch/armv7/start.S
@@ -8,7 +8,7 @@
 .section .init
 interrupt_vector_table:
 ivt_reset:     b _start        @ 0x00 Reset
-ivt_undef:     b .             @ 0x04 #UD
+ivt_undef:     b Undef_Handler @ 0x04 #UD
 ivt_svc:       b SVC_Handler   @ 0x08 SVC (used to be called SWI)
 ivt_prefetch:  b PrefetchAbort @ 0x0C Prefetch abort
 ivt_data:      b DataAbort     @ 0x10 Data abort
@@ -18,26 +18,51 @@ ivt_fiq:    b .             @ 0x1C FIQ (Fast interrupt)
 
 .globl _start
 _start:
+       ldr r2, =UART0_PADDR
+       mov r1, #'A'
+       str r1, [r2]    
+
        ldr r0, =kernel_table0-KERNEL_BASE
        mcr p15, 0, r0, c2, c0, 1       @ Set TTBR1 to r0
        mcr p15, 0, r0, c2, c0, 0       @ Set TTBR0 to r0 too (for identity)
 
+       mov r1, #'c'
+       str r1, [r2]    
+
        mov r0, #1
        mcr p15, 0, r0, c2, c0, 2       @ Set TTCR to 1 (50/50 split)
+
+       mov r1, #'e'
+       str r1, [r2]    
        
        mov r0, #3
        mcr p15, 0, r0, c3, c0, 0       @ Set Domain 0 to Manager
 
+       mov r1, #'s'
+       str r1, [r2]    
+
        @ Enable VMSA
        mrc p15, 0, r0, c1, c0, 0
        orr r0, r0, #1
        orr r0, r0, #1 << 23
+       mvn r1, #1 << 2
+       and r0, r0, r1
        mcr p15, 0, r0, c1, c0, 0
 
+       @ HACK! Disable caching
+       mrc p15, 0, r1, c1, c0, 0
+
+       ldr r2, =0xF1000000
+       mov r1, #'s'
+       str r1, [r2]    
+
        @ Enable access faults on domains 0 & 1
        mov r0, #0x55   @ 01010101b
        mcr p15, 0, r0, c3, c0, 0
 
+       mov r1, #'2'
+       str r1, [r2]    
+
        @
        @ Check for security extensions
        @
@@ -51,6 +76,8 @@ _start:
        orreq r0, #0x2000
        mcreq p15, 0, r0, c1, c0, 0
 
+       mov r1, #'-'
+       str r1, [r2]    
 
        @ Prepare for interrupts
        cps #18 @ IRQ Mode
@@ -59,12 +86,33 @@ _start:
        ldr sp, =abortstack+0x1000
        cps #19
 
-       ldr sp, =0x80000000-4   @ Set up stack (top of user range)
+       mov r1, #'a'
+       str r1, [r2]    
+       mov r1, #'r'
+       str r1, [r2]    
+       mov r1, #'m'
+       str r1, [r2]    
+       mov r1, #13
+       str r1, [r2]    
+       mov r1, #10
+       str r1, [r2]    
+
+.extern bss_start
+.extern bss_size_div_4
+.zero_bss:
+       ldr r0, =bss_start
+       ldr r1, =bss_end
+       mov r3, #0
+.zero_bss_loop:
+       str r3, [r0],#4
+       cmp r0, r1
+       bls .zero_bss_loop
+
+.goto_c:
+       ldr sp, =0x80000000-8   @ Set up stack (top of user range)
        ldr r0, =kmain
        mov pc, r0
 1:     b 1b    @ Infinite loop
-_ptr_kmain:
-       .long kmain
 
 .comm irqstack, 0x1000 @ ; 4KiB Stack
 .comm abortstack, 0x1000       @ ; 4KiB Stack
@@ -160,17 +208,27 @@ DataAbort:
 .globl PrefetchAbort
 PrefetchAbort:
        sub lr, #4      @ Adjust LR to the correct value
-@      srsdb sp!, #19  @ Switch to supervisor mode (DDI0406B D1.6.5) (actually SRSFD)
+       srsdb sp!, #23  @ Switch to supervisor mode (DDI0406B D1.6.5) (actually SRSFD)
 @      cpsid ifa, #19
-@      PUSH_GPRS
+       PUSH_GPRS
 
        ldr r0, =csAbort_Tag
        ldr r1, =csPrefetchAbort_Fmt
-       mov r2, lr
-       mrc p15, 0, r3, c5, c0, 0       @ Read IFSR (Instruction Fault Address Register) into R3
-       ldr r4, =Log_Error
-       blx r4
-       b .
+#      mov r2, lr
+       mrc p15, 0, r2, c6, c0, 2       @ Read IFAR (Instruction Fault Address Register) into R3
+       mrc p15, 0, r3, c5, c0, 1       @ Read IFSR (Instruction Fault Status Register) into R3
+       ldr r5, =Log_Error
+       blx r5
+
+.loop:
+       wfi
+       b .loop
+.globl Undef_Handler
+Undef_Handler:
+       wfi
+       b Undef_Handler
+
+
 
 .section .rodata
 csIRQ_Tag:
@@ -305,3 +363,5 @@ kernel_exception_map:
 stack:
        .space MM_KSTACK_SIZE, 0        @ Original kernel stack
 
+// vim: ts=8 ft=armv7
+