#include <mm_virt.h>
#include <threads_int.h>
#include <proc.h>
+#include <hal_proc.h>
// === CONSTANTS ===
#define PHYS_BITS 52 // TODO: Move out
void MM_int_ClonePageEnt( Uint64 *Ent, void *NextLevel, tVAddr Addr, int bTable );
int MM_PageFault(tVAddr Addr, Uint ErrorCode, tRegs *Regs);
void MM_int_DumpTablesEnt(tVAddr RangeStart, size_t Length, tPAddr Expected);
-void MM_DumpTables(tVAddr Start, tVAddr End);
+//void MM_DumpTables(tVAddr Start, tVAddr End);
int MM_GetPageEntryPtr(tVAddr Addr, BOOL bTemp, BOOL bAllocate, BOOL bLargePage, tPAddr **Pointer);
int MM_MapEx(tVAddr VAddr, tPAddr PAddr, BOOL bTemp, BOOL bLarge);
// int MM_Map(tVAddr VAddr, tPAddr PAddr);
void MM_Unmap(tVAddr VAddr);
void MM_int_ClearTableLevel(tVAddr VAddr, int LevelBits, int MaxEnts);
-void MM_ClearUser(void);
+//void MM_ClearUser(void);
int MM_GetPageEntry(tVAddr Addr, tPAddr *Phys, Uint *Flags);
// === GLOBALS ===
*/
int MM_PageFault(tVAddr Addr, Uint ErrorCode, tRegs *Regs)
{
+// Log_Debug("MMVirt", "Addr = %p, ErrorCode = %x", Addr, ErrorCode);
+
+ // Catch reserved bits first
+ if( ErrorCode & 0x8 )
+ {
+ Log_Warning("MMVirt", "Reserved bits trashed!");
+ Log_Warning("MMVirt", "PML4 Ent = %P", PAGEMAPLVL4(Addr>>39));
+ if( !(PAGEMAPLVL4(Addr>>39) & PF_PRESENT) ) goto print_done;
+ Log_Warning("MMVirt", "PDP Ent = %P", PAGEDIRPTR(Addr>>30));
+ if( !(PAGEDIRPTR(Addr>>30) & PF_PRESENT) ) goto print_done;
+ Log_Warning("MMVirt", "PDir Ent = %P", PAGEDIR(Addr>>21));
+ if( !(PAGEDIR(Addr>>21) & PF_PRESENT) ) goto print_done;
+ Log_Warning("MMVirt", "PTable Ent = %P", PAGETABLE(Addr>>12));
+ if( !(PAGETABLE(Addr>>12) & PF_PRESENT) ) goto print_done;
+ print_done:
+
+ for(;;);
+ }
+
// TODO: Implement Copy-on-Write
#if 1
if( PAGEMAPLVL4(Addr>>39) & PF_PRESENT
Warning("User Pagefault: Instruction at %04x:%p accessed %p",
Regs->CS, Regs->RIP, Addr);
__asm__ __volatile__ ("sti"); // Restart IRQs
+ Error_Backtrace(Regs->RIP, Regs->RBP);
Threads_SegFault(Addr);
return 0;
}
return ret;
}
+/**
+ * \brief Check if the provided buffer is valid
+ * \return Boolean valid
+ */
+int MM_IsValidBuffer(tVAddr Addr, size_t Size)
+{
+ int bIsUser;
+ Uint64 pml4, pdp, dir, tab;
+
+ Size += Addr & (PAGE_SIZE-1);
+ Addr &= ~(PAGE_SIZE-1);
+ Addr &= ((1UL << 48)-1); // Clap to address space
+
+ pml4 = Addr >> 39;
+ pdp = Addr >> 30;
+ dir = Addr >> 21;
+ tab = Addr >> 12;
+
+ if( !(PAGEMAPLVL4(pml4) & 1) ) return 0;
+ if( !(PAGEDIRPTR(pdp) & 1) ) return 0;
+ if( !(PAGEDIR(dir) & 1) ) return 0;
+ if( !(PAGETABLE(tab) & 1) ) return 0;
+
+ bIsUser = !!(PAGETABLE(tab) & PF_USER);
+
+ while( Size >= PAGE_SIZE )
+ {
+ if( (tab & 511) == 0 )
+ {
+ dir ++;
+ if( ((dir >> 9) & 511) == 0 )
+ {
+ pdp ++;
+ if( ((pdp >> 18) & 511) == 0 )
+ {
+ pml4 ++;
+ if( !(PAGEMAPLVL4(pml4) & 1) ) return 0;
+ }
+ if( !(PAGEDIRPTR(pdp) & 1) ) return 0;
+ }
+ if( !(PAGEDIR(dir) & 1) ) return 0;
+ }
+
+ if( !(PAGETABLE(tab) & 1) ) return 0;
+ if( bIsUser && !(PAGETABLE(tab) & PF_USER) ) return 0;
+
+ tab ++;
+ Size -= PAGE_SIZE;
+ }
+ return 1;
+}
+
// --- Hardware Mappings ---
/**
* \brief Map a range of hardware pages
{
// Skip addresses:
// 320 0xFFFFA.... - Kernel Stacks
- if( i == 320 ) continue;
+ if( i == MM_KSTACK_BASE>>39 ) continue;
// 509 0xFFFFFE0.. - Fractal mapping
- if( i == 508 ) continue;
+ if( i == MM_FRACTAL_BASE>>39 ) continue;
// 510 0xFFFFFE8.. - Temp fractal mapping
- if( i == 509 ) continue;
+ if( i == MM_TMPFRAC_BASE>>39 ) continue;
TMPMAPLVL4(i) = PAGEMAPLVL4(i);
if( TMPMAPLVL4(i) & 1 )