PCI_OC_SCSI = 0x010000\r
};\r
\r
+typedef enum ePCI_BARTypes tPCI_BARType;\r
+\r
+enum ePCI_BARTypes\r
+{\r
+ PCI_BARTYPE_IO,\r
+ PCI_BARTYPE_MEM, // Any memory type\r
+ PCI_BARTYPE_MEMP, // Prefetchable memory\r
+ PCI_BARTYPE_MEMNP, // Non-prefetchable memory\r
+ PCI_BARTYPE_MEM32, // 32-bit memory\r
+ PCI_BARTYPE_MEM64 // 64-bit memory\r
+};\r
+\r
+#define PCI_CMD_IOENABLE (1 << 0)\r
+#define PCI_CMD_MEMENABLE (1 << 1)\r
+#define PCI_CMD_BUSMASTER (1 << 2) // Device can behave as a bus master\r
+#define PCI_CMD_SPECIALCYCLES (1 << 3) // Can monitor 'Special Cycle' operations\r
+#define PCI_CMD_WRAINVAL (1 << 4) // Memory 'Write and Invalidate' can be generated\r
+#define PCI_CMD_VGAPALSNOOP (1 << 5) // VGA Palette Snoop enabled\r
+#define PCI_CMD_PARITYERRRESP (1 << 6) // Pairity Error Response (suppress PERR# generation)\r
+#define PCI_CMD_SERRENABLE (1 << 8) // Enable SERR# Driver\r
+#define PCI_CMD_FASTBACKBACK (1 << 9) // Fast Back-Back Enable\r
+#define PCI_CMD_INTDISABLE (1 <<10) // Disable generation of INTx# signals\r
+\r
typedef int tPCIDev;\r
\r
/**\r
extern Uint32 PCI_ConfigRead(tPCIDev id, int Offset, int Size);\r
extern void PCI_ConfigWrite(tPCIDev id, int Offset, int Size, Uint32 Value);\r
\r
+extern Uint16 PCI_SetCommand(tPCIDev id, Uint16 SBits, Uint16 CBits);\r
extern Uint8 PCI_GetIRQ(tPCIDev id);\r
extern Uint32 PCI_GetBAR(tPCIDev id, int BAR);\r
+extern Uint64 PCI_GetValidBAR(tPCIDev id, int BAR, tPCI_BARType BARType);\r
//extern Uint16 PCI_AssignPort(tPCIDev id, int bar, int count);\r
\r
#endif\r