* e1000.c
* - Intel 8254x Network Card Driver (core)
*/
-#define DEBUG 1
+#define DEBUG 0
#define VERSION VER2(0,1)
#include <acess.h>
#include "e1000.h"
// Allocate card array
gaE1000_Cards = calloc(sizeof(tCard), card_count);
if( !gaE1000_Cards ) {
+ Log_Warning("E1000", "Allocation of %i card structures failed", card_count);
return MODULE_ERR_MALLOC;
}
for( int id = -1, i = 0; (id = PCI_GetDevice(cardtype->Vendor, cardtype->Device, i)) != -1; i ++ )
{
tCard *card = &gaE1000_Cards[card_idx++];
- Uint32 mmiobase = PCI_GetBAR(id, 0);
- if( mmiobase & (1|8) ) {
+ card->MMIOBasePhys = PCI_GetValidBAR(id, 0, PCI_BARTYPE_MEMNP);
+ if( !card->MMIOBasePhys ) {
Log_Warning("E1000", "Dev %i: BAR0 should be non-prefetchable memory", id);
continue;
}
- const int addrsize = (mmiobase>>1) & 3;
- if( addrsize == 0 ) {
- // Standard 32-bit
- card->MMIOBasePhys = mmiobase & ~0xF;
- }
- else if( addrsize == 2 ) {
- // 64-bit
- card->MMIOBasePhys = (mmiobase & ~0xF) | ((Uint64)PCI_GetBAR(id, 1)<<32);
- }
- else {
- Log_Warning("E1000", "Dev %i: Unknown memory address size %i", id, (mmiobase>>1)&3);
- continue;
- }
card->IRQ = PCI_GetIRQ(id);
IRQ_AddHandler(card->IRQ, E1000_IRQHandler, card);
-
+ PCI_SetCommand(id, PCI_CMD_MEMENABLE|PCI_CMD_BUSMASTER, 0);
+
Log_Debug("E1000", "Card %i: %P IRQ %i", card_idx, card->MMIOBasePhys, card->IRQ);
if( E1000_int_InitialiseCard(card) ) {
+ Log_Warning("E1000", "Initialisation of card #%i failed", card_idx);
return MODULE_ERR_MALLOC;
}
int txd = first_txd;
while( (idx = IPStack_Buffer_GetBuffer(Buffer, idx, &len, &ptr)) != -1 )
{
+ //Debug_HexDump("E100 SendPacket", ptr, len);
if( MM_GetPhysAddr(ptr) + len-1 != MM_GetPhysAddr((char*)ptr + len-1) )
{
size_t remlen = PAGE_SIZE - ((tVAddr)ptr & (PAGE_SIZE-1));
Card->TXDescs[last_txd].CMD |= TXD_CMD_EOP|TXD_CMD_IDE|TXD_CMD_IFCS;
Card->TXSrcBuffers[last_txd] = Buffer;
- // Trigger TX
- IPStack_Buffer_LockBuffer(Buffer);
- LOG("Triggering TX - Buffers[%i]=%p", last_txd, Buffer);
- REG32(Card, REG_TDT) = Card->FirstFreeTXD;
- Mutex_Release(&Card->lTXDescs);
+ __sync_synchronize();
+ #if DEBUG
{
volatile tTXDesc *txdp = Card->TXDescs + last_txd;
LOG("%p %P: %llx %x %x", txdp, MM_GetPhysAddr((void*)txdp), txdp->Buffer, txdp->Length, txdp->CMD);
LOG("%p %P: %llx %x %x", txdp, MM_GetPhysAddr((void*)txdp), txdp->Buffer, txdp->Length, txdp->CMD);
MM_FreeTemp( (void*)txdp_base);
}
+ #endif
+ // Trigger TX
+ IPStack_Buffer_LockBuffer(Buffer);
+ LOG("Triggering TX - Buffers[%i]=%p", last_txd, Buffer);
+ REG32(Card, REG_TDT) = Card->FirstFreeTXD;
+ Mutex_Release(&Card->lTXDescs);
LOG("Waiting for TX to complete");
// Wait for completion (lock will block, then release straight away)
{
LOG("No completed TXDs");
}
- }
-
+ }
+
if( icr & ICR_LSC )
{
// Link status change
LOG("nPackets = %i", nPackets);
}
- icr &= ~(ICR_RXT0|ICR_LSC|ICR_TXQE|ICR_TXDW);
+ // Transmit Descriptor Low Threshold hit
+ if( icr & ICR_TXD_LOW )
+ {
+
+ }
+
+ // Receive Descriptor Minimum Threshold Reached
+ // - We're reading too slow
+ if( icr & ICR_RXDMT0 )
+ {
+ LOG("RX descs running out");
+ }
+
+ icr &= ~(ICR_RXT0|ICR_LSC|ICR_TXQE|ICR_TXDW|ICR_TXD_LOW|ICR_RXDMT0);
if( icr )
Log_Warning("E1000", "Unhandled ICR bits 0x%x", icr);
}