#ifndef _AHCI__AHCI_HW_H_
#define _AHCI__AHCI_HW_H_
+#include "sata.h"
+
#define AHCI_CAP_S64A (1 << 31) // Supports 64-bit addressing
#define AHCI_CAP_SNCQ (1 << 30) // Supports Native Command Queuing
#define AHCI_CAP_SXS (1 << 5) // Support External SATA
} Ports[32];
} PACKED;
-struct sAHCI_FIS_DMASetup
-{
- Uint32 unk[7];
-} PACKED;
-struct sAHCI_FIS_PIOSetup
-{
- Uint32 unk[5];
-} PACKED;
-struct sAHCI_FIS_D2HRegister
-{
- Uint32 unk[5];
-} PACKED;
-struct sAHCI_FIS_SDB
-{
- Uint32 unk[2];
-} PACKED;
-
struct sAHCI_RcvdFIS
{
- struct sAHCI_FIS_DMASetup DSFIS;
+ struct sSATA_FIS_DMASetup DSFIS;
Uint32 _pad1[1];
- struct sAHCI_FIS_PIOSetup PSFIS;
+ struct sSATA_FIS_PIOSetup PSFIS;
Uint32 _pad2[3];
- struct sAHCI_FIS_D2HRegister RFIS;
+ struct sSATA_FIS_D2HRegister RFIS;
Uint32 _pad3[1];
- struct sAHCI_FIS_SDB SDBFIS;
+ struct sSATA_FIS_SDB SDBFIS;
Uint32 UFIS[64/4];
Uint32 _redvd[(0x100 - 0xA0) / 4];
} PACKED;
Uint32 PRDBC;
Uint32 CTBA; // 128-byte alignment
Uint32 CTBAU;
- Uint32 resdv[4];
+ union {
+ struct {
+ struct sThread *Thread;
+ struct sAHCI_CmdTable *TablePtr;
+ } PACKED Ptrs;
+ Uint32 resdv[4];
+ } Resvd;
} PACKED;
struct sAHCI_CmdEnt
Uint32 DBC; // Data byte count (31: IOC, 21:0 count) 0=1, 1=2, ...
} PACKED;
+struct sAHCI_CmdTable
+{
+ Uint32 CFIS[64/4];
+ Uint32 ACMD[16/4];
+ Uint32 _resvd[0x30/4];
+ struct sAHCI_CmdEnt PRDT[0x80/16];
+} PACKED;
+
#endif