Merge branch 'master' of github.com:thepowersgang/acess2

[tpg/acess2.git] / KernelLand / Modules / USB / EHCI / ehci.h

diff --git a/KernelLand/Modules/USB/EHCI/ehci.h b/KernelLand/Modules/USB/EHCI/ehci.h
index 431b039..120c2f4 100644 (file)
--- a/KernelLand/Modules/USB/EHCI/ehci.h
+++ b/KernelLand/Modules/USB/EHCI/ehci.h
@@ -8,6 +8,14 @@
 #ifndef _EHCI_H_
 #define _EHCI_H_
 
+typedef struct sEHCI_CapRegs   tEHCI_CapRegs;
+typedef struct sEHCI_OpRegs    tEHCI_OpRegs;
+typedef struct sEHCI_iTD       tEHCI_iTD;
+typedef struct sEHCI_siTD      tEHCI_siTD;
+typedef struct sEHCI_qTD       tEHCI_qTD;
+typedef struct sEHCI_QH        tEHCI_QH;
+typedef struct sEHCI_Controller        tEHCI_Controller;
+
 struct sEHCI_CapRegs
 {
        Uint8   CapLength;      // Byte offset of Operational registers
@@ -152,5 +160,71 @@ struct sEHCI_OpRegs
        Uint32  PortSC[15];
 };
 
+#define USBCMD_Run     0x0001
+#define USBCMD_HCReset 0x0002
+#define USBCMD_PeriodicEnable  0x0010
+#define USBCMD_AsyncEnable     0x0020
+
+#define USBINTR_IOC    0x0001
+#define USBINTR_Error  0x0002
+#define USBINTR_PortChange     0x0004
+#define USBINTR_FrameRollover  0x0008
+#define USBINTR_HostSystemError        0x0010
+#define USBINTR_AsyncAdvance   0x0020
+
+struct sEHCI_iTD
+{
+       Uint32  Link;
+       struct {
+               Uint16  Offset;
+               Uint16  LengthSts;
+       } Transactions[8];
+       // -- 0 --
+       // 0:6  - Device
+       // 7    - Reserved
+       // 8:11 - Endpoint
+       // -- 1 --
+       // 0:10 - Max packet size
+       // 11   - IN/OUT
+       Uint32  BufferPointers[8];      // Page aligned, low 12 bits are overloaded
+};
+
+struct sEHCI_siTD
+{
+       Uint32  Link;
+       Uint32  Dest;
+       Uint32  uFrame;
+       Uint32  StatusLength;
+       Uint32  Page0;
+       Uint32  Page1;
+       Uint32  BackLink;
+};
+
+struct sEHCI_qTD
+{
+       Uint32  Link;
+       Uint32  Link2;  // Used when there's a short packet
+       Uint32  Token;
+       Uint32  Pages[5];       //First has offset in low 12 bits
+};
+
+struct sEHCI_QH
+{
+       Uint32  HLink;  // Horizontal link
+       Uint32  Endpoint;
+       Uint32  EndpointExt;
+       Uint32  CurrentTD;
+       tEHCI_qTD       Overlay;
+};
+
+struct sEHCI_Controller
+{
+       tPAddr  PhysBase;
+       tEHCI_CapRegs   *CapRegs;
+       tEHCI_OpRegs    *OpRegs;
+
+       Uint32  *PeriodicQueue;
+};
+
 #endif