// === TYPES ===
typedef struct sUHCI_Controller tUHCI_Controller;
+typedef struct sUHCI_EndpointInfo tUHCI_EndpointInfo;
typedef struct sUHCI_ExtraTDInfo tUHCI_ExtraTDInfo;
typedef struct sUHCI_TD tUHCI_TD;
void *CallbackPtr;
};
+struct sUHCI_EndpointInfo
+{
+ unsigned MaxPacketSize : 12;
+ unsigned Type : 3;
+ unsigned Tgl : 1;
+};
+
+#define TD_CTL_IOC (1 << 24)
+#define TD_CTL_ACTIVE (1 << 23)
+#define TD_CTL_STALLED (1 << 22)
+#define TD_CTL_DATABUFERR (1 << 21)
+#define TD_CTL_BABBLE (1 << 20)
+#define TD_CTL_NAK (1 << 19)
+#define TD_CTL_CRCERR (1 << 18)
+#define TD_CTL_BITSTUFF (1 << 17)
+#define TD_CTL_RESERVED (1 << 16)
+
struct sUHCI_TD
{
/**
{
tUHCI_ExtraTDInfo *ExtraInfo;
char bActive; // Allocated
- Uint8 period_entry; // index + 1, 0 = non-interrupt, 1 = offset 0
+ Uint8 QueueIndex; // QH, 0-127 are interrupt, 128 undef, 129 Control, 130 Bulk
char bFreePointer; // Free \a BufferPointer once done
} _info;
} __attribute__((aligned(16)));
*/
Uint32 Next;
-
/**
* \brief Next Entry in list
*
tUSBHub *RootHub;
/**
+ * \brief Load in bytes on each interrupt queue
*/
-// int FrameLoads[1024];
+ int InterruptLoad[128];
tPAddr PhysTDQHPage;
struct
{
// 127 Interrupt Queue Heads
// - 4ms -> 256ms range of periods
+ tUHCI_QH InterruptQHs[0];
tUHCI_QH InterruptQHs_256ms[64];
tUHCI_QH InterruptQHs_128ms[32];
tUHCI_QH InterruptQHs_64ms [16];
tUHCI_TD LocalTDPool[ (4096-(128+2)*sizeof(tUHCI_QH)) / sizeof(tUHCI_TD) ];
} *TDQHPage;
+
+ struct {
+ tUHCI_EndpointInfo EndpointInfo[16];
+ } *DevInfo[256];
};
// === ENUMERATIONS ===