}
else {
// Bit 0 is left set as a flag to other functions
- LOG("gATA_BusMasterBase = 0x%x", gATA_BusMasterBase & ~1);
+ LOG("gATA_BusMasterBase = IO 0x%x", gATA_BusMasterBase & ~1);
}
// Register IRQs and get Buffers
// Enable controllers
outb(IDE_PRI_BASE+1, 1);
outb(IDE_SEC_BASE+1, 1);
+ outb(IDE_PRI_CTRL, 0);
+ outb(IDE_SEC_CTRL, 0);
// Make sure interrupts are ACKed
ATA_int_BusMasterWriteByte(2, 0x4);
#if 1
if( cont == 0 ) {
- outb(base+IDE_PRI_CTRL, 4);
+ outb(IDE_PRI_CTRL, 4);
IO_DELAY();
- outb(base+IDE_PRI_CTRL, 0);
+ outb(IDE_PRI_CTRL, 0);
}
else {
- outb(base+IDE_SEC_CTRL, 4);
+ outb(IDE_SEC_CTRL, 4);
IO_DELAY();
- outb(base+IDE_SEC_CTRL, 0);
+ outb(IDE_SEC_CTRL, 0);
}
#endif
LOG("Status byte = 0x%02x, Controller Status = 0x%02x",
val, ATA_int_BusMasterReadByte(cont * 8 + 2));
- if( gaATA_IRQs[cont] == 0 ) {
-
+ if( gaATA_IRQs[cont] == 0 )
+ {
+ if( ATA_int_BusMasterReadByte(cont * 8 + 2) & 0x4 ) {
+ Log_Error("ATA", "BM Status reports an interrupt, but none recieved");
+ ATA_int_BusMasterWriteByte(cont*8 + 2, 4); // Clear interrupt
+ memcpy( Buffer, gATA_Buffers[cont], Count*SECTOR_SIZE );
+ Mutex_Release( &glaATA_ControllerLock[ cont ] );
+ LEAVE('i', 0);
+ return 0;
+ }
+
#if 1
Debug_HexDump("ATA", Buffer, 512);
#endif