Automatic commit. Thu Aug 9 17:00:03 WST 2012

[matches/honours.git] / research / TCS / 2012-08-09 / checklist

diff --git a/research/TCS/2012-08-09/checklist b/research/TCS/2012-08-09/checklist
index 7f273a6..ba1cff6 100644 (file)
--- a/research/TCS/2012-08-09/checklist
+++ b/research/TCS/2012-08-09/checklist
@@ -1,23 +1,25 @@
-# File opened at 2012-08-09 10:59:38.865710
+# File opened at 2012-08-09 16:10:28.641737
 # Accelerating Voltage = 38.4
-# Focus Voltage = 0.17
-# Deflection Voltage = 1.346
+# Focus Voltage = -0.185
+# Deflection Voltage = 1.347
 # Venault Voltage = 12.0
 # Initial Voltage = Sweep
-# Heating Current = 1.140
-# Heating Voltage = aasdf
-# Chamber Pressure = 3.89e-8
+# Heating Current = 1.141
+# Heating Voltage = 1.46
+# Chamber Pressure = 4.78e-8
 # 610B Zero = 0.00
 # 602 Zero = 0.00
 # 610B Scale = 1e-7 x 0.03
 # 602 Scale = 1e-5 x 0.3
-# 602 0.1 Battery = 8.40
-# 602 0.03 Battery = 7.85
-# 602 0.01 Battery = 8.05
-# 602 0.003 Battery = 8.00
-# 602 0.001 Battery = 8.10
+# 602 0.1 Battery = 8.3
+# 602 0.03 Battery = 7.75
+# 602 0.01 Battery = 7.95
+# 602 0.003 Battery = 7.95
+# 602 0.001 Battery = 7.70
 # ADC Regulator = 3.30
-# Title = Testing
-# Comment = adsf
-# Data = TEST
-# Parameters last checked = 2012-08-09 10:59:38.865447
+# Sample = Au on Si (60s 3.1A + 120 3.2A + 300s 3.5A ~1e-7mbar)
+# Title = Au on Si (8 min)
+# Comment = First sample; doing sweeps for sample with increasing thickness of Au.
+# Data = time DAC ADC4(Is) ADC4_sigma ADC5(Ie) ADC5_sigma
+# Parameters last checked = 2012-08-09 16:10:28.641461
+# File closed at 2012-08-09 16:10:28.642262