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Kernel/armv7 - Debugging, fixed TLB issues with a HACK!
author
John Hodge
<
[email protected]
>
Sat, 14 Jan 2012 13:08:13 +0000
(21:08 +0800)
committer
John Hodge
<
[email protected]
>
Sat, 14 Jan 2012 13:08:13 +0000
(21:08 +0800)
Kernel/arch/armv7/main.c
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|
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|
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Kernel/arch/armv7/mm_virt.c
patch
|
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|
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Kernel/arch/armv7/proc.S
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Kernel/arch/armv7/proc.c
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Kernel/arch/armv7/start.S
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diff --git
a/Kernel/arch/armv7/main.c
b/Kernel/arch/armv7/main.c
index
eb9f1a6
..
248c17c
100644
(file)
--- a/
Kernel/arch/armv7/main.c
+++ b/
Kernel/arch/armv7/main.c
@@
-43,8
+43,12
@@
int kmain(void)
//
LogF("Moving to arch-independent init\n");
//
LogF("Moving to arch-independent init\n");
+ #if PLATFORM_is_tegra2
+ System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=Tegra2Vid");
+ #else
System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=PL110");
System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=PL110");
-// System_Init("/Acess=initrd:");
+ #endif
+// System_Init("Acess2.armv7.bin /Acess=initrd:");
//TODO:
LogF("End of kmain(), for(;;) Threads_Sleep();\n");
for(;;)
//TODO:
LogF("End of kmain(), for(;;) Threads_Sleep();\n");
for(;;)
diff --git
a/Kernel/arch/armv7/mm_virt.c
b/Kernel/arch/armv7/mm_virt.c
index
d74313f
..
7ab7f61
100644
(file)
--- a/
Kernel/arch/armv7/mm_virt.c
+++ b/
Kernel/arch/armv7/mm_virt.c
@@
-37,7
+37,8
@@
typedef struct
#define FRACTAL(table1, addr) ((table1)[ (0xFF8/4*1024) + ((addr)>>22)])
#define USRFRACTAL(addr) (*((Uint32*)(0x7FDFF000) + ((addr)>>22)))
#define TLBIALL() __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0))
#define FRACTAL(table1, addr) ((table1)[ (0xFF8/4*1024) + ((addr)>>22)])
#define USRFRACTAL(addr) (*((Uint32*)(0x7FDFF000) + ((addr)>>22)))
#define TLBIALL() __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0))
-#define TLBIMVA(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1" : : "r" (addr))
+#define TLBIMVA(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c8, c7, 1;dsb;isb" : : "r" ((addr)&~0xFFF):"memory")
+#define DCCMVAC(addr) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((addr)&~0xFFF))
// === PROTOTYPES ===
void MM_int_GetTables(tVAddr VAddr, Uint32 **Table0, Uint32 **Table1);
// === PROTOTYPES ===
void MM_int_GetTables(tVAddr VAddr, Uint32 **Table0, Uint32 **Table1);
@@
-163,7
+164,9
@@
int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi)
if( (*desc & 3) == 1 ) LEAVE_RET('i', 1);
if( pi->PhysAddr == 0 ) {
*desc = 0;
if( (*desc & 3) == 1 ) LEAVE_RET('i', 1);
if( pi->PhysAddr == 0 ) {
*desc = 0;
- TLBIMVA(VAddr & 0xFFFFF000);
+ TLBIMVA( VAddr );
+ DCCMVAC( (tVAddr) desc );
+ TLBIALL();
LEAVE('i', 0);
return 0;
}
LEAVE('i', 0);
return 0;
}
@@
-174,7
+177,9
@@
int MM_int_SetPageInfo(tVAddr VAddr, tMM_PageInfo *pi)
if( pi->bShared) *desc |= 1 << 10; // S
*desc |= (pi->AP & 3) << 4; // AP
*desc |= ((pi->AP >> 2) & 1) << 9; // APX
if( pi->bShared) *desc |= 1 << 10; // S
*desc |= (pi->AP & 3) << 4; // AP
*desc |= ((pi->AP >> 2) & 1) << 9; // APX
- TLBIMVA(VAddr & 0xFFFFF000);
+ TLBIMVA( VAddr );
+ TLBIALL();
+ DCCMVAC( (tVAddr) desc );
LEAVE('i', 0);
return 0;
}
LEAVE('i', 0);
return 0;
}
@@
-482,7
+487,6
@@
void MM_Deallocate(tVAddr VAddr)
tMM_PageInfo pi;
if( MM_int_GetPageInfo(VAddr, &pi) ) return ;
tMM_PageInfo pi;
if( MM_int_GetPageInfo(VAddr, &pi) ) return ;
-
if( pi.PhysAddr == 0 ) return;
MM_DerefPhys(pi.PhysAddr);
if( pi.PhysAddr == 0 ) return;
MM_DerefPhys(pi.PhysAddr);
@@
-671,13
+675,15
@@
tPAddr MM_Clone(void)
memcpy(tmp_page, (void*)sp, 0x1000);
MM_FreeTemp( (tVAddr) tmp_page );
}
memcpy(tmp_page, (void*)sp, 0x1000);
MM_FreeTemp( (tVAddr) tmp_page );
}
-
+
MM_FreeTemp( (tVAddr)table );
}
MM_FreeTemp( (tVAddr)new_lvl1_1 );
MM_FreeTemp( (tVAddr)new_lvl1_2 );
MM_FreeTemp( (tVAddr)table );
}
MM_FreeTemp( (tVAddr)new_lvl1_1 );
MM_FreeTemp( (tVAddr)new_lvl1_2 );
+// Log("MM_Clone: ret = %P", ret);
+
return ret;
}
return ret;
}
diff --git
a/Kernel/arch/armv7/proc.S
b/Kernel/arch/armv7/proc.S
index
4d7c89f
..
531de29
100644
(file)
--- a/
Kernel/arch/armv7/proc.S
+++ b/
Kernel/arch/armv7/proc.S
@@
-47,7
+47,7
@@
SwitchTask:
tst r1, r1
mcrne p15, 0, r1, c2, c0, 0 @ Set TTBR0 to r0
mov r1, #0
tst r1, r1
mcrne p15, 0, r1, c2, c0, 0 @ Set TTBR0 to r0
mov r1, #0
- mcrne p15, 0, r1, c8, c7, 0 @
Invalidate all (HACK! But it fixes things)
+ mcrne p15, 0, r1, c8, c7, 0 @
TLBIALL - Invalidate all
@ Restore SP
mov sp, r0
@ Restore SP
mov sp, r0
@@
-99,4
+99,6
@@
Proc_int_DropToUser:
.section .rodata
csProc_CloneInt_NewTaskMessage:
.section .rodata
csProc_CloneInt_NewTaskMessage:
- .asciz "New task"
+ .asciz "New task PC=%p, R4=%p, sp=%p"
+csProc_CloneInt_OldTaskMessage:
+ .asciz "Parent task PC=%p, R4=%p, SP=%p"
diff --git
a/Kernel/arch/armv7/proc.c
b/Kernel/arch/armv7/proc.c
index
b5a867c
..
c3cb226
100644
(file)
--- a/
Kernel/arch/armv7/proc.c
+++ b/
Kernel/arch/armv7/proc.c
@@
-208,6
+208,7
@@
void Proc_Reschedule(void)
next->SavedState.IP, next->SavedState.SP, next->MemState.Base,
next->SavedState.UserSP
);
next->SavedState.IP, next->SavedState.SP, next->MemState.Base,
next->SavedState.UserSP
);
+
Log("Requested by %p", __builtin_return_address(0));
gpCurrentThread = next;
Log("Requested by %p", __builtin_return_address(0));
gpCurrentThread = next;
diff --git
a/Kernel/arch/armv7/start.S
b/Kernel/arch/armv7/start.S
index
1c1e0c8
..
8d9f3e4
100644
(file)
--- a/
Kernel/arch/armv7/start.S
+++ b/
Kernel/arch/armv7/start.S
@@
-8,7
+8,7
@@
.section .init
interrupt_vector_table:
ivt_reset: b _start @ 0x00 Reset
.section .init
interrupt_vector_table:
ivt_reset: b _start @ 0x00 Reset
-ivt_undef: b
.
@ 0x04 #UD
+ivt_undef: b
Undef_Handler
@ 0x04 #UD
ivt_svc: b SVC_Handler @ 0x08 SVC (used to be called SWI)
ivt_prefetch: b PrefetchAbort @ 0x0C Prefetch abort
ivt_data: b DataAbort @ 0x10 Data abort
ivt_svc: b SVC_Handler @ 0x08 SVC (used to be called SWI)
ivt_prefetch: b PrefetchAbort @ 0x0C Prefetch abort
ivt_data: b DataAbort @ 0x10 Data abort
@@
-45,8
+45,13
@@
_start:
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1
orr r0, r0, #1 << 23
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1
orr r0, r0, #1 << 23
+ mvn r1, #1 << 2
+ and r0, r0, r1
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c1, c0, 0
+ @ HACK! Disable caching
+ mrc p15, 0, r1, c1, c0, 0
+
ldr r2, =0xF1000000
mov r1, #'s'
str r1, [r2]
ldr r2, =0xF1000000
mov r1, #'s'
str r1, [r2]
@@
-215,7
+220,15
@@
PrefetchAbort:
ldr r5, =Log_Error
blx r5
ldr r5, =Log_Error
blx r5
- b .
+.loop:
+ wfi
+ b .loop
+.globl Undef_Handler
+Undef_Handler:
+ wfi
+ b Undef_Handler
+
+
.section .rodata
csIRQ_Tag:
.section .rodata
csIRQ_Tag:
UCC
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