ld-acess.exe
AcessKernel
AcessKernel.exe
+Makefile.BuildNum
# Core ARMv7 modules
-MODULES += armv7/GIC
MODULES += Filesystems/InitRD
include $(ACESSDIR)/BuildConf/armv7/default.mk
ARM_CPUNAME = cortex-a8
+MODULES += armv7/GIC
MODULES += Input/PS2KbMouse
MODULES += Display/PL110
include $(ACESSDIR)/BuildConf/armv7/default.mk
ARM_CPUNAME = cortex-a9
+MODULES += armv7/GIC
MODULES += Display/Tegra2Vid
MODULES += USB/Core USB/EHCI
A_OBJ = start.ao main.o lib.o lib.ao time.o pci.o debug.o
A_OBJ += mm_phys.o mm_virt.o proc.o proc.ao
-A_OBJ += vpci_$(PLATFORM).o
+A_OBJ += vpci_$(PLATFORM).o platform_$(PLATFORM).o
#main.c: Makefile.BuildNum.$(ARCH)
extern void Heap_Install(void);
extern void Threads_Init(void);
extern void System_Init(const char *Commandline);
+extern void Time_Setup(void);
// === PROTOTYPES ===
int kmain(void);
//
LogF("Moving to arch-independent init\n");
#if PLATFORM_is_tegra2
- System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=Tegra2Vid");
+ System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=Tegra2Vid -USB_EHCI:C5000000-14,C5004000-15");
#else
System_Init("Acess2.armv7.bin /Acess=initrd: -VTerm:Video=PL110");
#endif
#include <hal_proc.h>
#define TRACE_MAPS 0
-#define TRACE_COW 1
+#define TRACE_COW 0
#define AP_KRW_ONLY 1 // Kernel page
#define AP_KRO_ONLY 5 // Kernel RO page
--- /dev/null
+/*
+ * Acess2 Kernel ARMv7 Port
+ * - By John Hodge (thePowersGang)
+ *
+ * platform_realviewpb.c
+ * - RealviewPB core code
+ */
+#include <acess.h>
+
+// === PROTOTYPES ===
+void Time_Setup(void);
+
+// === GLOBALS ===
+tPAddr gGIC_DistributorAddr = 0x1e001000;
+tPAddr gGIC_InterfaceAddr = 0x1e000000;
+
+// === CODE ===
+void Time_Setup(void)
+{
+ // TODO:
+}
--- /dev/null
+/*
+ * Acess2 Kernel ARMv7 Port
+ * - By John Hodge (thePowersGang)
+ *
+ * platform_tegra2.c
+ * - Tegra2 Core code
+ */
+#include <acess.h>
+#include "platform_tegra2.h"
+
+// === CONSTANTS ===
+#define TIMER0_INT (0*32+0) // Pri #0
+#define TIMER1_INT (0*32+1) // Pri #1
+#define TIMER2_INT (1*32+9) // Sec #9
+#define TIMER3_INT (1*32+10) // Sec #10
+
+// === Imports ===
+extern volatile Sint64 giTimestamp;
+extern volatile Uint64 giTicks;
+extern volatile Uint64 giPartMiliseconds;
+extern void Timer_CallTimers(void);
+
+// === PROTORTYPES ===
+void Timer_IRQHandler_SysClock(int IRQ, void *_unused);
+void Time_Setup(void);
+
+// === GLOBALS ===
+// - Addresses for the GIC to use
+tPAddr gGIC_InterfaceAddr = 0x50040000;
+tPAddr gGIC_DistributorAddr = 0x50041000;
+// - Map of timer registers
+struct sTimersMap *gpTimersMap;
+// - Interrupt controller code commented out, because the Tegra2 also has a GIC
+#if 0
+struct sIRQMap gpIRQMap;
+#endif
+
+// === CODE ===
+
+// -- Timers --
+void Timer_IRQHandler_SysClock(int IRQ, void *_unused)
+{
+ giTimestamp += 100;
+ gpTimersMap->TMR0.PCR_0 = (1<<31);
+}
+
+void Time_Setup(void)
+{
+ gpTimersMap = (void*)MM_MapHWPages(0x60005000, 1);
+ // Timer 1 (used for system timekeeping)
+ IRQ_AddHandler(0*32+0, Timer_IRQHandler_SysClock, NULL);
+ gpTimersMap->TMR0.PTV_0 = (1<31)|(1<30)|(100*1000); // enable, periodic, 100 ms
+}
+
+#if 0
+// -- Interrupt Controller --
+void IRQ_CtrlrHandler(struct sIRQRegs *Ctrlr, int Ofs)
+{
+ // Primary CPU only?
+ // TODO:
+}
+
+void IRQ_RootHandler(void)
+{
+ IRQ_CtrlrHandler(&gpIRQMap->Pri, 0*32);
+ IRQ_CtrlrHandler(&gpIRQMap->Sec, 1*32);
+ IRQ_CtrlrHandler(&gpIRQMap->Tri, 2*32);
+ IRQ_CtrlrHandler(&gpIRQMap->Quad, 3*32);
+}
+
+void IRQ_Setup(void)
+{
+ gpIRQMap = (void*)MM_MapHWPages(0x60004000, 1);
+
+ gpIRQHandler = IRQ_RootHandler;
+}
+#endif
--- /dev/null
+/*
+ * Acess2 Kernel ARMv7 Port
+ * - By John Hodge (thePowersGang)
+ *
+ * platform_tegra2.c
+ * - Tegra2 Core code
+ */
+#ifndef _PLATFORM__TEGRA2_H_
+#define _PLATFORM__TEGRA2_H_
+
+struct sTimerRegs
+{
+ Uint32 PTV_0; // Control / Target value
+ Uint32 PCR_0; // Current value / IRQ clear
+};
+struct sTimersMap
+{
+ struct sTimerRegs TMR0;
+ struct sTimerRegs TMR1;
+ // TMRUS
+ char _padding[ 0x50-0x10 ];
+
+ struct sTimerRegs TMR2;
+ struct sTimerRegs TMR3;
+};
+
+#if 0
+struct sIRQRegs
+{
+ Uint32 VIRQ_CPU;
+ Uint32 VIRQ_COP;
+ Uint32 VFIQ_CPU;
+ Uint32 VFIQ_COP;
+ Uint32 ISR;
+ Uint32 FIR; // Force interrupt status
+ Uint32 FIR_SET; // Set bit in FIR
+ Uint32 FIR_CLR; // Clear bit in FIR
+ Uint32 CPU_IER; // RO - Interrupt Enable register
+ Uint32 CPU_IER_SET;
+ Uint32 CPU_IER_CLR;
+ Uint32 CPU_IEP; // 1 = FIQ
+ Uint32 COP_IER; // RO - Interrupt Enable register
+ Uint32 COP_IER_SET;
+ Uint32 COP_IER_CLR;
+ Uint32 COP_IEP; // 1 = FIQ
+};
+struct sArbGntRegs
+{
+ Uint32 CPU_Status;
+ Uint32 CPU_Enable;
+ Uint32 COP_Status;
+ Uint32 COP_Enable;
+};
+struct sIRQMap
+{
+ struct sIRQRegs Pri;
+ struct sArbGntRegs Arb;
+ char _pad1[0x100-sizeof(struct sIRQRegs)-sizeof(struct sIRQRegs)];
+ struct sIRQRegs Sec;
+ char _pad2[0x100-sizeof(struct sIRQRegs)];
+ struct sIRQRegs Tri;
+ char _pad3[0x100-sizeof(struct sIRQRegs)];
+ struct sIRQRegs Quad;
+};
+#endif
+
+#endif
+
// === GLOBALS ===
tVPCI_Device gaVPCI_Devices[] = {
+ // NOTE: USB Controllers moved to command line arguments
+ #if 0
{
.Vendor=0x0ACE,.Device=0x1100,
- .Class = 0x0C032000, // Serial, USB, ECHI
+ .Class = 0x0C032100, // Serial, USB, ECHI
.BARs = {0xC5000000,0,0,0,0,0},
.IRQ = 0*32+20,
},
.BARs = {0xC5008000,0,0,0,0,0},
.IRQ = 4*32+1,
}
+ #endif
};
int giVPCI_DeviceCount = sizeof(gaVPCI_Devices)/sizeof(gaVPCI_Devices[0]);
// === IMPORTS ===
extern char gKernelEnd[];
-extern void Heap_Install(void);
extern void MM_PreinitVirtual(void);
extern void MM_Install(int NPMemRanges, tPMemMapEnt *PMemRanges);
extern void MM_InstallVirtual(void);
// Adjust Multiboot structure address
mbInfo = (void*)( (Uint)MbInfoPtr + KERNEL_BASE );
gsBootCmdLine = (char*)( (Uint)mbInfo->CommandLine + KERNEL_BASE);
- // TODO: ref above?
nPMemMapEnts = Multiboot_LoadMemoryMap(mbInfo, KERNEL_BASE, pmemmap, MAX_PMEMMAP_ENTS,
KERNEL_LOAD, (tVAddr)&gKernelEnd - KERNEL_BASE
);
Log_Log("Arch", "Starting VFS...");
VFS_Init();
+ // Multiboot_InitFramebuffer(mbInfo);
+
gaArch_BootModules = Multiboot_LoadModules(mbInfo, KERNEL_BASE, &giArch_NumBootModules);
*(Uint16*)(KERNEL_BASE|0xB8000) = 0x1F00|'Z';
tTID Proc_NewKThread(void (*Fcn)(void*), void *Data)
{
Uint rsp;
- tThread *newThread, *cur;
+ tThread *newThread;
- cur = Proc_GetCurThread();
newThread = Threads_CloneTCB(0);
if(!newThread) return -1;
*/
tThread *Proc_SpawnWorker(void (*Fcn)(void*), void *Data)
{
- tThread *new, *cur;
+ tThread *new;
Uint stack_contents[3];
- cur = Proc_GetCurThread();
-
// Create new thread
new = Threads_CloneThreadZero();
if(!new) {
devinfo->revision = gaVPCI_Devices[i].Class & 0xFF;\r
devinfo->class = gaVPCI_Devices[i].Class >> 8;\r
snprintf(devinfo->Name, sizeof(devinfo->Name), "%02x.%02x:%x", 0xFF, i, 0);\r
+ \r
+ #if LIST_DEVICES\r
+ Log_Log("PCI", "Device %i,%i:%i %06x => 0x%04x:0x%04x Rev %i",\r
+ 0xFF, i, 0, devinfo->class,\r
+ devinfo->vendor, devinfo->device, devinfo->revision);\r
+ #endif\r
\r
for(int j = 0; j < 256/4; j ++ )\r
- devinfo->ConfigCache[i] = VPCI_Read(&gaVPCI_Devices[i], j*4, 4);\r
+ devinfo->ConfigCache[j] = VPCI_Read(&gaVPCI_Devices[i], j*4, 4);\r
\r
memset(&devinfo->Node, 0, sizeof(devinfo->Node));\r
devinfo->Node.Inode = giPCI_DeviceCount;\r
case 0: // Vendor[0:15], Device[16:31]
tmp_dword = (Dev->Vendor) | (Dev->Device << 16);
break;
+ // 1: Command[0:15], Status[16:31]
case 2: // Class Code
tmp_dword = Dev->Class;
break;
- // 1: Command[0:15], Status[16:31]
// 3: Cache Line Size, Latency Timer, Header Type, BIST
- // 4-9: BARs
+ case 4 ... 9: // 4-9: BARs
+ tmp_dword = Dev->BARs[ (Offset>>2) - 4 ];
+ break;
// 10: Unused (Cardbus CIS Pointer)
// 11: Subsystem Vendor ID, Subsystem ID
// 12: Expansion ROM Address
// 14: Reserved
// 15: Interrupt Line, Interrupt Pin, Min Grant, Max Latency
default:
- tmp_dword = Dev->Read(Dev->Ptr, Offset >> 2);
+ if( Dev->Read )
+ tmp_dword = Dev->Read(Dev->Ptr, Offset >> 2);
break;
}
return ;
}
- tmp_dword = Dev->Read(Dev->Ptr, Offset>>2);
+ if( Size != 4 && Dev->Read )
+ tmp_dword = Dev->Read(Dev->Ptr, Offset>>2);
+ else
+ tmp_dword = 0;
switch(Size)
{
case 4: tmp_dword = 0; break;
break;
}
tmp_dword |= Data << ((Offset&3)*8);
- Dev->Write(Dev->Ptr, Offset>>2, tmp_dword);
+ if( Dev->Write )
+ Dev->Write(Dev->Ptr, Offset>>2, tmp_dword);
}
extern int strpos8(const char *str, Uint32 search);
extern void itoa(char *buf, Uint64 num, int base, int minLength, char pad);
extern int atoi(const char *string);
+extern unsigned long long strtoull(const char *str, char **end, int base);
+extern unsigned long strtoul(const char *str, char **end, int base);
+extern signed long long strtoll(const char *str, char **end, int base);
+extern signed long strtol(const char *str, char **end, int base);
extern int ParseInt(const char *string, int *Val);
extern int ReadUTF8(const Uint8 *str, Uint32 *Val);
extern int WriteUTF8(Uint8 *str, Uint32 Val);
extern void StartupPrint(const char *String);
extern void System_Init(char *Commandline);
extern void Threads_Init(void);
+extern void Heap_Install(void);
#endif
#define RANDOM_SPRUCE 0xf12b039
// === PROTOTYPES ===
+#if 0
unsigned long long strtoull(const char *str, char **end, int base);
unsigned long strtoul(const char *str, char **end, int base);
signed long long strtoll(const char *str, char **end, int base);
signed long strtol(const char *str, char **end, int base);
-#if 0
int atoi(const char *string);
int ParseInt(const char *string, int *Val);
void itoa(char *buf, Uint64 num, int base, int minLength, char pad);
#if 0
tVFS_Handle *VFS_GetHandle(int FD);
#endif
+inline void _ReferenceNode(tVFS_Node *Node);
int VFS_AllocHandle(int FD, tVFS_Node *Node, int Mode);
// === GLOBALS ===
Uint32 *gpTegra2Vid_IOMem;
tPAddr gTegra2Vid_FramebufferPhys;
void *gpTegra2Vid_Framebuffer;
+void *gpTegra2Vid_Cursor;
// -- Misc
tDrvUtil_Video_BufInfo gTegra2Vid_DrvUtil_BufInfo;
tVideo_IOCtl_Pos gTegra2Vid_CursorPos;
Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x (%s)", i, gpTegra2Vid_IOMem[i],
(csaTegra2Vid_RegisterNames[i] ? csaTegra2Vid_RegisterNames[i] : "-"));
}
+
+void Tegra2Vid_int_DumpRegisters(void)
+{
+ Log_Debug("Tegra2Vid", "Display CMD Registers");
+ for( int i = 0x000; i <= 0x01A; i ++ ) _dumpreg(i);
+ for( int i = 0x028; i <= 0x043; i ++ ) _dumpreg(i);
+ Log_Debug("Tegra2Vid", "Display COM Registers");
+ for( int i = 0x300; i <= 0x329; i ++ ) _dumpreg(i);
+ Log_Debug("Tegra2Vid", "Display DISP Registers");
+ for( int i = 0x400; i <= 0x446; i ++ ) _dumpreg(i);
+ for( int i = 0x480; i <= 0x484; i ++ ) _dumpreg(i);
+ for( int i = 0x4C0; i <= 0x4C1; i ++ ) _dumpreg(i);
+ Log_Debug("Tegra2Vid", "WINC_A Registers");
+ for( int i = 0x700; i <= 0x714; i ++ ) _dumpreg(i);
+ Log_Debug("Tegra2Vid", "WINBUF_A");
+ for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i);
+}
+
/**
*/
int Tegra2Vid_Install(char **Arguments)
// KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments);
gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4);
+
#if DUMP_REGISTERS
- {
- Log_Debug("Tegra2Vid", "Display CMD Registers");
- for( int i = 0x000; i <= 0x01A; i ++ ) _dumpreg(i);
- for( int i = 0x028; i <= 0x043; i ++ ) _dumpreg(i);
- Log_Debug("Tegra2Vid", "Display COM Registers");
- for( int i = 0x300; i <= 0x329; i ++ ) _dumpreg(i);
- Log_Debug("Tegra2Vid", "Display DISP Registers");
- for( int i = 0x400; i <= 0x446; i ++ ) _dumpreg(i);
- for( int i = 0x480; i <= 0x484; i ++ ) _dumpreg(i);
- for( int i = 0x4C0; i <= 0x4C1; i ++ ) _dumpreg(i);
- Log_Debug("Tegra2Vid", "WINC_A Registers");
- for( int i = 0x700; i <= 0x714; i ++ ) _dumpreg(i);
- Log_Debug("Tegra2Vid", "WINBUF_A");
- for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i);
- }
+ Tegra2Vid_int_DumpRegisters();
#endif
// HACK!!!
}
#endif
+#if 0
giTegra2Vid_FramebufferSize =
(gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0]&0xFFFF)
*(gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0]>>16)*4;
gpTegra2Vid_IOMem[DC_WINBUF_A_START_ADDR_0],
(giTegra2Vid_FramebufferSize+PAGE_SIZE-1)/PAGE_SIZE
);
- memset(gpTegra2Vid_Framebuffer, 0xFF, 0x1000);
+ Log_Debug("Tegra2Vid", "gpTegra2Vid_Framebuffer = %p", gpTegra2Vid_Framebuffer);
+ memset(gpTegra2Vid_Framebuffer, 0xFF, giTegra2Vid_FramebufferSize);
+#endif
#if 0
gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] = (1 << 30);
gTegra2Vid_DrvUtil_BufInfo.Depth = 32;
gTegra2Vid_DrvUtil_BufInfo.Width = 1680;
gTegra2Vid_DrvUtil_BufInfo.Height = 1050;
-#else
+ gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ;
+#elif 0
gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 13; // Could be 13 (BGR/RGB)
gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] =
gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4;
gTegra2Vid_DrvUtil_BufInfo.Width = 1024;
gTegra2Vid_DrvUtil_BufInfo.Height = 768;
gTegra2Vid_DrvUtil_BufInfo.Framebuffer = gpTegra2Vid_Framebuffer;
-#endif
gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ;
+#endif
+ gpTegra2Vid_Cursor = (void*)MM_AllocDMA(1, 26, NULL);
-// Tegra2Vid_int_SetMode(4);
+ Tegra2Vid_int_SetMode(0);
DevFS_AddDevice( &gTegra2Vid_DriverStruct );
LEAVE_RET('i', 0);
// DEBUG!!!
- mode->width = 1024;
- mode->height = 768;
+ mode->id = 1; mode->width = 1680; mode->height = 1050;
+ mode->id = 0; mode->width = 1024; mode->height = 768;
+
+ // DEBUG!
+ for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i);
break;
ret = 0;
for( int i = 0; i < ciTegra2Vid_ModeCount; i ++ )
{
int area;
- if(mode->width == caTegra2Vid_Modes[i].W && mode->height == caTegra2Vid_Modes[i].H) {
+ if(mode->width == caTegra2Vid_Modes[i].W
+ && mode->height == caTegra2Vid_Modes[i].H) {
mode->id = i;
ret = 1;
break;
DrvUtil_Video_RemoveCursor( &gTegra2Vid_DrvUtil_BufInfo );
gTegra2Vid_CursorPos = *(tVideo_IOCtl_Pos*)Data;
+ // TODO: Set DC_DISP_CURSOR_POSITION_0
+ // TODO: Set DC_DISP_CURSOR_FOREGROUND_0 etc from image?
if(gTegra2Vid_DrvUtil_BufInfo.BufferFormat == VIDEO_BUFFMT_TEXT)
DrvUtil_Video_DrawCursor(
&gTegra2Vid_DrvUtil_BufInfo,
{
const struct sTegra2_Disp_Mode *mode = &caTegra2Vid_Modes[Mode];
int w = mode->W, h = mode->H; // Horizontal/Vertical Active
- gpTegra2Vid_IOMem[DC_DISP_FRONT_PORCH_0] = (mode->VFP << 16) | mode->HFP;
+ gpTegra2Vid_IOMem[DC_DISP_REF_TO_SYNC_0] = (1 << 16) | 11; // TODO: <--
gpTegra2Vid_IOMem[DC_DISP_SYNC_WIDTH_0] = (mode->HS << 16) | mode->HS;
gpTegra2Vid_IOMem[DC_DISP_BACK_PORCH_0] = (mode->VBP << 16) | mode->HBP;
gpTegra2Vid_IOMem[DC_DISP_DISP_ACTIVE_0] = (mode->H << 16) | mode->W;
+ gpTegra2Vid_IOMem[DC_DISP_FRONT_PORCH_0] = (mode->VFP << 16) | mode->HFP;
+ gpTegra2Vid_IOMem[DC_DISP_DISP_COLOR_CONTROL_0] = 0x8; // BASE888 - TODO: useful?
gpTegra2Vid_IOMem[DC_WIN_A_POSITION_0] = 0;
gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0] = (h << 16) | w;
- gpTegra2Vid_IOMem[DC_DISP_DISP_COLOR_CONTROL_0] = 0x8; // BASE888
gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB)
gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = (h << 16) | w;
+ gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] = w * 4;
+ gpTegra2Vid_IOMem[DC_WIN_A_DV_CONTROL_0] = 0;
+
+ gpTegra2Vid_IOMem[DC_DISP_BORDER_COLOR_0] = 0x70F010;
Log_Debug("Tegra2Vid", "Mode %i (%ix%i) selected", Mode, w, h);
giTegra2Vid_FramebufferSize = w*h*4;
- // TODO: Does this need RAM or unmapped space?
+ // Uses RAM I think
gpTegra2Vid_Framebuffer = (void*)MM_AllocDMA(
(giTegra2Vid_FramebufferSize + PAGE_SIZE-1) / PAGE_SIZE,
32,
&gTegra2Vid_FramebufferPhys
);
- // TODO: Catch allocation failures
+ if( !gpTegra2Vid_Framebuffer ) {
+ Log_Error("Tegra2Vid", "Can't allocate pages for 0x%x byte framebuffer",
+ giTegra2Vid_FramebufferSize);
+ return -1;
+ }
Log_Debug("Tegra2Vid", "0x%x byte framebuffer at %p (%P phys)",
giTegra2Vid_FramebufferSize,
gpTegra2Vid_Framebuffer,
}
gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ;
+ gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = GEN_ACT_REQ;
+
+ // DEBUG!
+ for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i);
return 0;
}
} caTegra2Vid_Modes[] = {
// TODO: VESA timings
{1024, 768, 58, 4, 58, 4, 58, 4}, // 1024x768 (reset), RtS=11,4
+ {1680,1050, 104, 1, 184, 3 , 288, 33}, // 1680x1050 @ 60Hz
// TV Timings
{720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
{720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
DC_WIN_A_DDA_INCREMENT_0,
DC_WIN_A_LINE_STRIDE_0,
DC_WIN_A_BUF_STRIDE_0,
+ _DC_WIN_A_70C,
DC_WIN_A_BUFFER_ADDR_MODE_0,
DC_WIN_A_DV_CONTROL_0,
DC_WIN_A_BLEND_NOKEY_0,
"DC_WIN_A_DDA_INCREMENT_0",
"DC_WIN_A_LINE_STRIDE_0",
"DC_WIN_A_BUF_STRIDE_0",
+ "-",
"DC_WIN_A_BUFFER_ADDR_MODE_0",
"DC_WIN_A_DV_CONTROL_0",
"DC_WIN_A_BLEND_NOKEY_0",
// TODO: Detect other forms of failure than "out of slots"
break ;
}
+ }
- // TODO: Register with the USB stack
+ for( int i = 0; Arguments[i]; i ++ )
+ {
+ char *pos = Arguments[i], *next;
+ LOG("pos = '%s'", pos);
+ tPAddr base = strtoull(pos, &next, 16);
+ if( base == 0 )
+ continue;
+ pos = next;
+ LOG("pos = '%s'", pos);
+ if( *pos++ != '-' )
+ continue;
+ LOG("pos = '%s'", pos);
+ int irq = strtol(pos, &next, 16);
+ if( irq == 0 )
+ continue ;
+ if( *next != 0 )
+ continue;
+ LOG("base=%x, irq=%i", base, irq);
+ if( EHCI_InitController(base, irq) )
+ {
+ continue ;
+ }
}
+
return 0;
}
}
// TODO: Error check
if( (cont->CapRegs->CapLength & 3) ) {
- Log_Warning("EHCI", "Controller at %P non-aligned op regs", BaseAddress);
+ Log_Warning("EHCI", "Controller at %P non-aligned op regs (%x)",
+ BaseAddress, cont->CapRegs->CapLength);
goto _error;
}
cont->OpRegs = (void*)( (Uint32*)cont->CapRegs + cont->CapRegs->CapLength / 4 );
// === IMPORTS ===
extern void *gpIRQHandler;
+extern tPAddr gGIC_DistributorAddr;
+extern tPAddr gGIC_InterfaceAddr;
// === TYPES ===
typedef void (*tIRQ_Handler)(int, void*);
MODULE_DEFINE(0, 0x100, armv7_GIC, GIC_Install, NULL, NULL);
Uint32 *gpGIC_DistributorBase;
Uint32 *gpGIC_InterfaceBase;
-tPAddr gGIC_DistributorAddr;
-tPAddr gGIC_InterfaceAddr;
tIRQ_Handler gaIRQ_Handlers[N_IRQS];
void *gaIRQ_HandlerData[N_IRQS];
// === CODE ===
int GIC_Install(char **Arguments)
{
- // Realview PB
- gGIC_InterfaceAddr = 0x1e000000;
- gGIC_DistributorAddr = 0x1e001000;
-
// Initialise
gpGIC_InterfaceBase = (void*)MM_MapHWPages(gGIC_InterfaceAddr, 1);
LOG("gpGIC_InterfaceBase = %p", gpGIC_InterfaceBase);
git.ucc.asn.au / tpg / acess2.git / commitdiff
UCC git Repository :: git.ucc.asn.au