* ARM7 Entrypoint
* arch/arm7/main.c
*/
+#define DEBUG 1
+
#include <acess.h>
#include <modules.h>
// === PROTOTYPES ===
int kmain(void);
+Uint32 ARMv7_int_HandleSyscalls(Uint32 Num, Uint32 *Args);
// === CODE ===
int kmain(void)
{
}
+Uint32 ARMv7_int_HandleSyscalls(Uint32 Num, Uint32 *Args)
+{
+ Uint32 ret = -1, err = 0;
+ Uint32 addr;
+ ENTER("iNum xArgs[0] xArgs[1] xArgs[2] xArgs[3]",
+ Num, Args[0], Args[1], Args[2], Args[3]
+ );
+ switch(Num)
+ {
+ case 1:
+ Log_Debug("ARMv7", "__clear_cache(%p, %p)", Args[0], Args[1]);
+ // Align
+ Args[0] &= ~0xFFF;
+ Args[1] += 0xFFF; Args[1] &= ~0xFFF;
+ // Invalidate!
+ for( addr = Args[0]; addr < Args[1]; addr += 0x1000 )
+ {
+ LOG("addr = %p", addr);
+ __asm__ __volatile__ (
+ "mcrlt p15, 0, %0, c7, c5, 1;\n\t"
+ "mcrlt p15, 0, %0, c7, c6, 1;\n\t"
+ :
+ : "r" (addr)
+ );
+ }
+ ret = 0;
+ break;
+ }
+ Args[0] = ret; // RetLow
+ Args[1] = 0; // RetHi
+ Args[2] = err; // Errno
+ LEAVE('x', ret);
+ return ret;
+}
+
{
tPAddr table;
Uint32 *tmp_map;
- Uint32 *cur = (void*)MM_TABLE0USER;
+ Uint32 *cur = (void*)MM_TABLE1USER;
// Uint32 *cur = &FRACTAL(MM_TABLE1USER,0);
int i;
for( i = 0; i < 1024; i ++ )
{
- switch(cur[i] & 3)
+// Log_Debug("MMVirt", "cur[%i] (%p) = %x", Table*256+i, &cur[Table*256+i], cur[Table*256+i]);
+ switch(cur[Table*256+i] & 3)
{
case 0: tmp_map[i] = 0; break;
case 1:
tmp_map[i] = 0;
- Log_Error("MMVirt", "TODO: Support large pages in MM_int_CloneTable");
+ Log_Error("MMVirt", "TODO: Support large pages in MM_int_CloneTable (%p)", (Table*256+i)*0x1000);
// Large page?
break;
case 2:
Uint32 *new_lvl1_1, *new_lvl1_2, *cur;
Uint32 *tmp_map;
int i;
+
+// MM_DumpTables(0, KERNEL_BASE);
ret = MM_AllocateRootTable();
Proc_CloneInt_new:
cps #18
- mov r0, #0
- mov r1, #0
- sub r1, #1
- bl MM_DumpTables
+@ mov r0, #0
+@ mov r1, #0
+@ sub r1, #1
+@ bl MM_DumpTables
@ ldr r0, =csProc_CloneInt_NewTaskMessage
@ bl Log
rfeia sp! @ Pop state (actually RFEFD)
.arm_specifics:
and r4, #0xFF
+ mov r0, r4 @ Number
+ mov r1, sp @ Arguments
+
+ ldr r4, =ARMv7_int_HandleSyscalls
+ blx r4
-@
-@ Cache invalidation
- cmp r4, #0x001
- bne 1f
- @ Page align
- mov r2, #0x1000
- sub r2, #1
- add r1, r2
- mvn r2, r2
- and r0, r2
- and r1, r2
- cmp r0, #0x78000000
- cmpls r1, #0x78000000
- movge r0, #-1
- movge r1, #0
- movge r2, #1
- bge .ret
-
-2:
- cmp r0, r1
- mcrlt p15, 0, r0, c7, c5, 1
- mcrlt p15, 0, r0, c7, c6, 1
- addlt r0, #0x1000
- blt 2b
- mov r0, #0
- mov r1, #0
- mov r2, #0
- b .ret
-1:
- mov r0, #-1
- mov r1, #0
- mov r2, #-1
-.ret:
add sp, #4*4
pop {r4-r12}
rfeia sp!