include $(ACESSDIR)/BuildConf/armv7/default.mk
-MODULES += Display/Tegra2
+MODULES += Display/Tegra2Vid
+++ /dev/null
-#
-#
-
-OBJ = main.o
-NAME = Tegra2
-
--include ../Makefile.tpl
+++ /dev/null
-/**\r
- * main.c\r
- * - Driver core\r
- */\r
-#define DEBUG 0\r
-#define VERSION ((0<<8)|10)\r
-#include <acess.h>\r
-#include <errno.h>\r
-#include <modules.h>\r
-#include <vfs.h>\r
-#include <fs_devfs.h>\r
-#include <drv_pci.h>\r
-#include <api_drv_video.h>\r
-#include <lib/keyvalue.h>\r
-#include <options.h> // ARM Arch\r
-#include "tegra2.h"\r
-\r
-#define ABS(a) ((a)>0?(a):-(a))\r
-\r
-// === PROTOTYPES ===\r
-// Driver\r
- int Tegra2Vid_Install(char **Arguments);\r
-void Tegra2Vid_Uninstall();\r
-// Internal\r
-// Filesystem\r
-Uint64 Tegra2Vid_Read(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer);\r
-Uint64 Tegra2Vid_Write(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer);\r
- int Tegra2Vid_IOCtl(tVFS_Node *node, int id, void *data);\r
-// -- Internals\r
- int Tegra2Vid_int_SetMode(int Mode);\r
-\r
-// === GLOBALS ===\r
-MODULE_DEFINE(0, VERSION, Video_Tegra2, Tegra2Vid_Install, NULL, NULL);\r
-tDevFS_Driver gTegra2Vid_DriverStruct = {\r
- NULL, "PL110",\r
- {\r
- .Read = Tegra2Vid_Read,\r
- .Write = Tegra2Vid_Write,\r
- .IOCtl = Tegra2Vid_IOCtl\r
- }\r
-};\r
-// -- Options\r
-tPAddr gTegra2Vid_PhysBase = TEGRA2VID_BASE;\r
- int gbTegra2Vid_IsVersatile = 1;\r
-// -- KeyVal parse rules\r
-const tKeyVal_ParseRules gTegra2Vid_KeyValueParser = {\r
- NULL,\r
- {\r
- {"Base", "P", &gTegra2Vid_PhysBase},\r
- {NULL, NULL, NULL}\r
- }\r
-};\r
-// -- Driver state\r
- int giTegra2Vid_CurrentMode = 0;\r
- int giTegra2Vid_BufferMode;\r
-size_t giTegra2Vid_FramebufferSize;\r
-Uint8 *gpTegra2Vid_IOMem;\r
-tPAddr gTegra2Vid_FramebufferPhys;\r
-void *gpTegra2Vid_Framebuffer;\r
-// -- Misc\r
-tDrvUtil_Video_BufInfo gTegra2Vid_DrvUtil_BufInfo;\r
-tVideo_IOCtl_Pos gTegra2Vid_CursorPos;\r
-\r
-// === CODE ===\r
-/**\r
- */\r
-int Tegra2Vid_Install(char **Arguments)\r
-{\r
-// KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments);\r
- \r
- gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4);\r
-\r
- Tegra2Vid_int_SetMode(4);\r
-\r
- DevFS_AddDevice( &gTegra2Vid_DriverStruct );\r
-\r
- return 0;\r
-}\r
-\r
-/**\r
- * \brief Clean up resources for driver unloading\r
- */\r
-void Tegra2Vid_Uninstall()\r
-{\r
-}\r
-\r
-/**\r
- * \brief Read from the framebuffer\r
- */\r
-Uint64 Tegra2Vid_Read(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer)\r
-{\r
- return 0;\r
-}\r
-\r
-/**\r
- * \brief Write to the framebuffer\r
- */\r
-Uint64 Tegra2Vid_Write(tVFS_Node *Node, Uint64 Offset, Uint64 Length, void *Buffer)\r
-{\r
- gTegra2Vid_DrvUtil_BufInfo.BufferFormat = giTegra2Vid_BufferMode;\r
- return DrvUtil_Video_WriteLFB(&gTegra2Vid_DrvUtil_BufInfo, Offset, Length, Buffer);\r
-}\r
-\r
-const char *csaTegra2Vid_IOCtls[] = {DRV_IOCTLNAMES, DRV_VIDEO_IOCTLNAMES, NULL};\r
-\r
-/**\r
- * \brief Handle messages to the device\r
- */\r
-int Tegra2Vid_IOCtl(tVFS_Node *Node, int ID, void *Data)\r
-{\r
- int ret = -2;\r
- ENTER("pNode iID pData", Node, ID, Data);\r
- \r
- switch(ID)\r
- {\r
- BASE_IOCTLS(DRV_TYPE_VIDEO, "PL110", VERSION, csaTegra2Vid_IOCtls);\r
-\r
- case VIDEO_IOCTL_SETBUFFORMAT:\r
- DrvUtil_Video_RemoveCursor( &gTegra2Vid_DrvUtil_BufInfo );\r
- ret = giTegra2Vid_BufferMode;\r
- if(Data) giTegra2Vid_BufferMode = *(int*)Data;\r
- if(gTegra2Vid_DrvUtil_BufInfo.BufferFormat == VIDEO_BUFFMT_TEXT)\r
- DrvUtil_Video_SetCursor( &gTegra2Vid_DrvUtil_BufInfo, &gDrvUtil_TextModeCursor );\r
- break;\r
- \r
- case VIDEO_IOCTL_GETSETMODE:\r
- if(Data)\r
- {\r
- int newMode;\r
- \r
- if( !CheckMem(Data, sizeof(int)) )\r
- LEAVE_RET('i', -1);\r
- \r
- newMode = *(int*)Data;\r
- \r
- if(newMode < 0 || newMode >= ciTegra2Vid_ModeCount)\r
- LEAVE_RET('i', -1);\r
-\r
- if(newMode != giTegra2Vid_CurrentMode)\r
- {\r
- giTegra2Vid_CurrentMode = newMode;\r
- Tegra2Vid_int_SetMode( newMode );\r
- }\r
- }\r
- ret = giTegra2Vid_CurrentMode;\r
- break;\r
- \r
- case VIDEO_IOCTL_FINDMODE:\r
- {\r
- tVideo_IOCtl_Mode *mode = Data;\r
- int closest, closestArea, reqArea = 0;\r
- if(!Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Mode)))\r
- LEAVE_RET('i', -1);\r
- if( mode->bpp != 32 )\r
- LEAVE_RET('i', 0);\r
- if( mode->flags != 0 )\r
- LEAVE_RET('i', 0);\r
-\r
- ret = 0;\r
-\r
- for( int i = 0; i < ciTegra2Vid_ModeCount; i ++ )\r
- {\r
- int area;\r
- if(mode->width == caTegra2Vid_Modes[i].W && mode->height == caTegra2Vid_Modes[i].H) {\r
- mode->id = i;\r
- ret = 1;\r
- break;\r
- }\r
- \r
- area = caTegra2Vid_Modes[i].W * caTegra2Vid_Modes[i].H;\r
- if(!reqArea) {\r
- reqArea = mode->width * mode->height;\r
- closest = i;\r
- closestArea = area;\r
- }\r
- else if( ABS(area - reqArea) < ABS(closestArea - reqArea) ) {\r
- closest = i;\r
- closestArea = area;\r
- }\r
- }\r
- \r
- if( ret == 0 )\r
- {\r
- mode->id = closest;\r
- ret = 1;\r
- }\r
- mode->width = caTegra2Vid_Modes[mode->id].W;\r
- mode->height = caTegra2Vid_Modes[mode->id].H;\r
- break;\r
- }\r
- \r
- case VIDEO_IOCTL_MODEINFO:\r
- {\r
- tVideo_IOCtl_Mode *mode = Data;\r
- if(!Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Mode)))\r
- LEAVE_RET('i', -1);\r
- if(mode->id < 0 || mode->id >= ciTegra2Vid_ModeCount)\r
- LEAVE_RET('i', 0);\r
- \r
-\r
- mode->bpp = 32;\r
- mode->flags = 0;\r
- mode->width = caTegra2Vid_Modes[mode->id].W;\r
- mode->height = caTegra2Vid_Modes[mode->id].H;\r
-\r
- ret = 1;\r
- break;\r
- }\r
- \r
- case VIDEO_IOCTL_SETCURSOR:\r
- if( !Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Pos)) )\r
- LEAVE_RET('i', -1);\r
-\r
- DrvUtil_Video_RemoveCursor( &gTegra2Vid_DrvUtil_BufInfo );\r
- \r
- gTegra2Vid_CursorPos = *(tVideo_IOCtl_Pos*)Data;\r
- if(gTegra2Vid_DrvUtil_BufInfo.BufferFormat == VIDEO_BUFFMT_TEXT)\r
- DrvUtil_Video_DrawCursor(\r
- &gTegra2Vid_DrvUtil_BufInfo,\r
- gTegra2Vid_CursorPos.x*giVT_CharWidth,\r
- gTegra2Vid_CursorPos.y*giVT_CharHeight\r
- );\r
- else\r
- DrvUtil_Video_DrawCursor(\r
- &gTegra2Vid_DrvUtil_BufInfo,\r
- gTegra2Vid_CursorPos.x,\r
- gTegra2Vid_CursorPos.y\r
- );\r
- break;\r
- \r
- default:\r
- LEAVE('i', -2);\r
- return -2;\r
- }\r
- \r
- LEAVE('i', ret);\r
- return ret;\r
-}\r
-\r
-//\r
-//\r
-//\r
-\r
-int Tegra2Vid_int_SetMode(int Mode)\r
-{\r
- const struct sTegra2_Disp_Mode *mode = &caTegra2Vid_Modes[Mode];\r
- int w = mode->W, h = mode->H; // Horizontal/Vertical Active\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_FRONT_PORCH_0) = (mode->VFP << 16) | mode->HFP; \r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_SYNC_WIDTH_0) = (mode->HS << 16) | mode->HS;\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_BACK_PORCH_0) = (mode->VBP << 16) | mode->HBP;\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_ACTIVE_0) = (mode->H << 16) | mode->W;\r
-\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_POSITION_0) = 0;\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (mode->H << 16) | mode->W;\r
- *(Uint8*)(gpTegra2Vid_IOMem + DC_WIN_A_COLOR_DEPTH_0) = 12; // Could be 13 (BGR/RGB)\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (mode->H << 16) | mode->W;\r
-\r
- if( !gpTegra2Vid_Framebuffer || w*h*4 != giTegra2Vid_FramebufferSize )\r
- {\r
- if( gpTegra2Vid_Framebuffer )\r
- {\r
- // TODO: Free framebuffer for reallocation\r
- }\r
-\r
- giTegra2Vid_FramebufferSize = w*h*4; \r
-\r
- gpTegra2Vid_Framebuffer = (void*)MM_AllocDMA(\r
- (giTegra2Vid_FramebufferSize + PAGE_SIZE-1) / PAGE_SIZE,\r
- 32,\r
- &gTegra2Vid_FramebufferPhys\r
- );\r
- // TODO: Catch allocation failures\r
- \r
- // Tell hardware\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_START_ADDR_0) = gTegra2Vid_FramebufferPhys;\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_V_OFFSET_0) = 0; // Y offset\r
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_H_OFFSET_0) = 0; // X offset\r
- }\r
-\r
- return 0;\r
-}\r
+++ /dev/null
-/*
- * Acess2 NVidia Tegra2 Display Driver
- * - By John Hodge (thePowersGang)
- *
- * tegra2.h
- * - Driver definitions
- */
-#ifndef _TEGRA2_DISP_H_
-#define _TEGRA2_DISP_H_
-
-#define TEGRA2VID_BASE 0x54200000 // 0x40000 Large (256 KB)
-
-const struct sTegra2_Disp_Mode
-{
- Uint16 W, H;
- Uint16 HFP, VFP;
- Uint16 HS, VS;
- Uint16 HBP, VBP;
-} caTegra2Vid_Modes[] = {
- // TODO: VESA timings
- {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
- {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
- {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
- {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
- {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
- // TODO: Can all but HA/VA be constant and those select the resolution?
-};
-const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
-
-enum eTegra2_Disp_Regs
-{
- DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
- DC_DISP_DISP_SIGNAL_OPTIONS1_0,
- DC_DISP_DISP_WIN_OPTIONS_0,
- DC_DISP_MEM_HIGH_PRIORITY_0,
- DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,
- DC_DISP_DISP_TIMING_OPTIONS_0,
- DC_DISP_REF_TO_SYNC_0,
- DC_DISP_SYNC_WIDTH_0,
- DC_DISP_BACK_PORCH_0,
- DC_DISP_DISP_ACTIVE_0,
- DC_DISP_FRONT_PORCH_0,
-
- DC_DISP_H_PULSE0_CONTROL_0,
-
- DC_WINC_A_COLOR_PALETTE_0 = 0x500,
- DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
- DC_WIN_A_WIN_OPTIONS_0 = 0x700,
- DC_WIN_A_BYTE_SWAP_0,
- DC_WIN_A_BUFFER_CONTROL_0,
- DC_WIN_A_COLOR_DEPTH_0,
- DC_WIN_A_POSITION_0,
- DC_WIN_A_SIZE_0,
- DC_WIN_A_PRESCALED_SIZE_0,
- DC_WIN_A_H_INITIAL_DDA_0,
- DC_WIN_A_V_INITIAL_DDA_0,
- DC_WIN_A_DDA_INCREMENT_0,
- DC_WIN_A_LINE_STRIDE_0,
- DC_WIN_A_BUF_STRIDE_0,
- DC_WIN_A_BUFFER_ADDR_MODE_0,
- DC_WIN_A_DV_CONTROL_0,
- DC_WIN_A_BLEND_NOKEY_0,
-
- DC_WINBUF_A_START_ADDR_0 = 0x800,
- DC_WINBUF_A_START_ADDR_NS_0,
- DC_WINBUF_A_ADDR_H_OFFSET_0,
- DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
- DC_WINBUF_A_ADDR_V_OFFSET_0,
- DC_WINBUF_A_ADDR_V_OFFSET_NS_0,
-};
-
-#endif
-
--- /dev/null
+#
+#
+
+OBJ = main.o
+NAME = Tegra2Vid
+
+-include ../Makefile.tpl
--- /dev/null
+/**\r
+ * main.c\r
+ * - Driver core\r
+ */\r
+#define DEBUG 0\r
+#define VERSION ((0<<8)|10)\r
+#include <acess.h>\r
+#include <errno.h>\r
+#include <modules.h>\r
+#include <vfs.h>\r
+#include <fs_devfs.h>\r
+#include <drv_pci.h>\r
+#include <api_drv_video.h>\r
+#include <lib/keyvalue.h>\r
+#include <options.h> // ARM Arch\r
+#include "tegra2.h"\r
+\r
+#define ABS(a) ((a)>0?(a):-(a))\r
+\r
+// === PROTOTYPES ===\r
+// Driver\r
+ int Tegra2Vid_Install(char **Arguments);\r
+void Tegra2Vid_Uninstall();\r
+// Internal\r
+// Filesystem\r
+Uint64 Tegra2Vid_Read(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer);\r
+Uint64 Tegra2Vid_Write(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer);\r
+ int Tegra2Vid_IOCtl(tVFS_Node *node, int id, void *data);\r
+// -- Internals\r
+ int Tegra2Vid_int_SetMode(int Mode);\r
+\r
+// === GLOBALS ===\r
+MODULE_DEFINE(0, VERSION, Tegra2Vid, Tegra2Vid_Install, NULL, NULL);\r
+tDevFS_Driver gTegra2Vid_DriverStruct = {\r
+ NULL, "Tegra2Vid",\r
+ {\r
+ .Read = Tegra2Vid_Read,\r
+ .Write = Tegra2Vid_Write,\r
+ .IOCtl = Tegra2Vid_IOCtl\r
+ }\r
+};\r
+// -- Options\r
+tPAddr gTegra2Vid_PhysBase = TEGRA2VID_BASE;\r
+ int gbTegra2Vid_IsVersatile = 1;\r
+// -- KeyVal parse rules\r
+const tKeyVal_ParseRules gTegra2Vid_KeyValueParser = {\r
+ NULL,\r
+ {\r
+ {"Base", "P", &gTegra2Vid_PhysBase},\r
+ {NULL, NULL, NULL}\r
+ }\r
+};\r
+// -- Driver state\r
+ int giTegra2Vid_CurrentMode = 0;\r
+ int giTegra2Vid_BufferMode;\r
+size_t giTegra2Vid_FramebufferSize;\r
+Uint32 *gpTegra2Vid_IOMem;\r
+tPAddr gTegra2Vid_FramebufferPhys;\r
+void *gpTegra2Vid_Framebuffer;\r
+// -- Misc\r
+tDrvUtil_Video_BufInfo gTegra2Vid_DrvUtil_BufInfo;\r
+tVideo_IOCtl_Pos gTegra2Vid_CursorPos;\r
+\r
+// === CODE ===\r
+/**\r
+ */\r
+int Tegra2Vid_Install(char **Arguments)\r
+{\r
+// KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments);\r
+ \r
+ gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4);\r
+\r
+ Tegra2Vid_int_SetMode(4);\r
+\r
+ DevFS_AddDevice( &gTegra2Vid_DriverStruct );\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Clean up resources for driver unloading\r
+ */\r
+void Tegra2Vid_Uninstall()\r
+{\r
+}\r
+\r
+/**\r
+ * \brief Read from the framebuffer\r
+ */\r
+Uint64 Tegra2Vid_Read(tVFS_Node *node, Uint64 off, Uint64 len, void *buffer)\r
+{\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * \brief Write to the framebuffer\r
+ */\r
+Uint64 Tegra2Vid_Write(tVFS_Node *Node, Uint64 Offset, Uint64 Length, void *Buffer)\r
+{\r
+ gTegra2Vid_DrvUtil_BufInfo.BufferFormat = giTegra2Vid_BufferMode;\r
+ return DrvUtil_Video_WriteLFB(&gTegra2Vid_DrvUtil_BufInfo, Offset, Length, Buffer);\r
+}\r
+\r
+const char *csaTegra2Vid_IOCtls[] = {DRV_IOCTLNAMES, DRV_VIDEO_IOCTLNAMES, NULL};\r
+\r
+/**\r
+ * \brief Handle messages to the device\r
+ */\r
+int Tegra2Vid_IOCtl(tVFS_Node *Node, int ID, void *Data)\r
+{\r
+ int ret = -2;\r
+ ENTER("pNode iID pData", Node, ID, Data);\r
+ \r
+ switch(ID)\r
+ {\r
+ BASE_IOCTLS(DRV_TYPE_VIDEO, "PL110", VERSION, csaTegra2Vid_IOCtls);\r
+\r
+ case VIDEO_IOCTL_SETBUFFORMAT:\r
+ DrvUtil_Video_RemoveCursor( &gTegra2Vid_DrvUtil_BufInfo );\r
+ ret = giTegra2Vid_BufferMode;\r
+ if(Data) giTegra2Vid_BufferMode = *(int*)Data;\r
+ if(gTegra2Vid_DrvUtil_BufInfo.BufferFormat == VIDEO_BUFFMT_TEXT)\r
+ DrvUtil_Video_SetCursor( &gTegra2Vid_DrvUtil_BufInfo, &gDrvUtil_TextModeCursor );\r
+ break;\r
+ \r
+ case VIDEO_IOCTL_GETSETMODE:\r
+ if(Data)\r
+ {\r
+ int newMode;\r
+ \r
+ if( !CheckMem(Data, sizeof(int)) )\r
+ LEAVE_RET('i', -1);\r
+ \r
+ newMode = *(int*)Data;\r
+ \r
+ if(newMode < 0 || newMode >= ciTegra2Vid_ModeCount)\r
+ LEAVE_RET('i', -1);\r
+\r
+ if(newMode != giTegra2Vid_CurrentMode)\r
+ {\r
+ giTegra2Vid_CurrentMode = newMode;\r
+ Tegra2Vid_int_SetMode( newMode );\r
+ }\r
+ }\r
+ ret = giTegra2Vid_CurrentMode;\r
+ break;\r
+ \r
+ case VIDEO_IOCTL_FINDMODE:\r
+ {\r
+ tVideo_IOCtl_Mode *mode = Data;\r
+ int closest, closestArea, reqArea = 0;\r
+ if(!Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Mode)))\r
+ LEAVE_RET('i', -1);\r
+ if( mode->bpp != 32 )\r
+ LEAVE_RET('i', 0);\r
+ if( mode->flags != 0 )\r
+ LEAVE_RET('i', 0);\r
+\r
+ ret = 0;\r
+\r
+ for( int i = 0; i < ciTegra2Vid_ModeCount; i ++ )\r
+ {\r
+ int area;\r
+ if(mode->width == caTegra2Vid_Modes[i].W && mode->height == caTegra2Vid_Modes[i].H) {\r
+ mode->id = i;\r
+ ret = 1;\r
+ break;\r
+ }\r
+ \r
+ area = caTegra2Vid_Modes[i].W * caTegra2Vid_Modes[i].H;\r
+ if(!reqArea) {\r
+ reqArea = mode->width * mode->height;\r
+ closest = i;\r
+ closestArea = area;\r
+ }\r
+ else if( ABS(area - reqArea) < ABS(closestArea - reqArea) ) {\r
+ closest = i;\r
+ closestArea = area;\r
+ }\r
+ }\r
+ \r
+ if( ret == 0 )\r
+ {\r
+ mode->id = closest;\r
+ ret = 1;\r
+ }\r
+ mode->width = caTegra2Vid_Modes[mode->id].W;\r
+ mode->height = caTegra2Vid_Modes[mode->id].H;\r
+ break;\r
+ }\r
+ \r
+ case VIDEO_IOCTL_MODEINFO:\r
+ {\r
+ tVideo_IOCtl_Mode *mode = Data;\r
+ if(!Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Mode)))\r
+ LEAVE_RET('i', -1);\r
+ if(mode->id < 0 || mode->id >= ciTegra2Vid_ModeCount)\r
+ LEAVE_RET('i', 0);\r
+ \r
+\r
+ mode->bpp = 32;\r
+ mode->flags = 0;\r
+ mode->width = caTegra2Vid_Modes[mode->id].W;\r
+ mode->height = caTegra2Vid_Modes[mode->id].H;\r
+\r
+ ret = 1;\r
+ break;\r
+ }\r
+ \r
+ case VIDEO_IOCTL_SETCURSOR:\r
+ if( !Data || !CheckMem(Data, sizeof(tVideo_IOCtl_Pos)) )\r
+ LEAVE_RET('i', -1);\r
+\r
+ DrvUtil_Video_RemoveCursor( &gTegra2Vid_DrvUtil_BufInfo );\r
+ \r
+ gTegra2Vid_CursorPos = *(tVideo_IOCtl_Pos*)Data;\r
+ if(gTegra2Vid_DrvUtil_BufInfo.BufferFormat == VIDEO_BUFFMT_TEXT)\r
+ DrvUtil_Video_DrawCursor(\r
+ &gTegra2Vid_DrvUtil_BufInfo,\r
+ gTegra2Vid_CursorPos.x*giVT_CharWidth,\r
+ gTegra2Vid_CursorPos.y*giVT_CharHeight\r
+ );\r
+ else\r
+ DrvUtil_Video_DrawCursor(\r
+ &gTegra2Vid_DrvUtil_BufInfo,\r
+ gTegra2Vid_CursorPos.x,\r
+ gTegra2Vid_CursorPos.y\r
+ );\r
+ break;\r
+ \r
+ default:\r
+ LEAVE('i', -2);\r
+ return -2;\r
+ }\r
+ \r
+ LEAVE('i', ret);\r
+ return ret;\r
+}\r
+\r
+//\r
+//\r
+//\r
+\r
+int Tegra2Vid_int_SetMode(int Mode)\r
+{\r
+ const struct sTegra2_Disp_Mode *mode = &caTegra2Vid_Modes[Mode];\r
+ int w = mode->W, h = mode->H; // Horizontal/Vertical Active\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_FRONT_PORCH_0) = (mode->VFP << 16) | mode->HFP; \r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_SYNC_WIDTH_0) = (mode->HS << 16) | mode->HS;\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_BACK_PORCH_0) = (mode->VBP << 16) | mode->HBP;\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_ACTIVE_0) = (mode->H << 16) | mode->W;\r
+\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_POSITION_0) = 0;\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (mode->H << 16) | mode->W;\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_COLOR_CONTROL_0) = 0x8; // BASE888\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_COLOR_DEPTH_0) = 12; // Could be 13 (BGR/RGB)\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (mode->H << 16) | mode->W;\r
+\r
+ Log_Debug("Tegra2Vid", "Mode %i (%ix%i) selected", Mode, w, h);\r
+\r
+ if( !gpTegra2Vid_Framebuffer || w*h*4 != giTegra2Vid_FramebufferSize )\r
+ {\r
+ if( gpTegra2Vid_Framebuffer )\r
+ {\r
+ // TODO: Free framebuffer for reallocation\r
+ }\r
+\r
+ giTegra2Vid_FramebufferSize = w*h*4; \r
+\r
+ gpTegra2Vid_Framebuffer = (void*)MM_AllocDMA(\r
+ (giTegra2Vid_FramebufferSize + PAGE_SIZE-1) / PAGE_SIZE,\r
+ 32,\r
+ &gTegra2Vid_FramebufferPhys\r
+ );\r
+ // TODO: Catch allocation failures\r
+ Log_Debug("Tegra2Vid", "0x%x byte framebuffer at %p (%P phys)",\r
+ giTegra2Vid_FramebufferSize,\r
+ gpTegra2Vid_Framebuffer,\r
+ gTegra2Vid_FramebufferPhys\r
+ );\r
+ \r
+ // Tell hardware\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_START_ADDR_0) = gTegra2Vid_FramebufferPhys;\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_V_OFFSET_0) = 0; // Y offset\r
+ *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_H_OFFSET_0) = 0; // X offset\r
+ }\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+/*
+ * Acess2 NVidia Tegra2 Display Driver
+ * - By John Hodge (thePowersGang)
+ *
+ * tegra2.h
+ * - Driver definitions
+ */
+#ifndef _TEGRA2_DISP_H_
+#define _TEGRA2_DISP_H_
+
+#define TEGRA2VID_BASE 0x54200000 // 0x40000 Large (256 KB)
+
+const struct sTegra2_Disp_Mode
+{
+ Uint16 W, H;
+ Uint16 HFP, VFP;
+ Uint16 HS, VS;
+ Uint16 HBP, VBP;
+} caTegra2Vid_Modes[] = {
+ // TODO: VESA timings
+ {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
+ {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
+ {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
+ {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
+ {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
+ // TODO: Can all but HA/VA be constant and those select the resolution?
+};
+const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
+
+enum eTegra2_Disp_Regs
+{
+ DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
+ DC_DISP_DISP_SIGNAL_OPTIONS1_0,
+ DC_DISP_DISP_WIN_OPTIONS_0,
+ DC_DISP_MEM_HIGH_PRIORITY_0,
+ DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,
+ DC_DISP_DISP_TIMING_OPTIONS_0,
+ DC_DISP_REF_TO_SYNC_0,
+ DC_DISP_SYNC_WIDTH_0,
+ DC_DISP_BACK_PORCH_0,
+ DC_DISP_DISP_ACTIVE_0,
+ DC_DISP_FRONT_PORCH_0,
+
+ DC_DISP_H_PULSE0_CONTROL_0,
+
+ DC_DISP_DISP_COLOR_CONTROL_0 = 0x430,
+
+ DC_WINC_A_COLOR_PALETTE_0 = 0x500,
+ DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
+ DC_WIN_A_WIN_OPTIONS_0 = 0x700,
+ DC_WIN_A_BYTE_SWAP_0,
+ DC_WIN_A_BUFFER_CONTROL_0,
+ DC_WIN_A_COLOR_DEPTH_0,
+ DC_WIN_A_POSITION_0,
+ DC_WIN_A_SIZE_0,
+ DC_WIN_A_PRESCALED_SIZE_0,
+ DC_WIN_A_H_INITIAL_DDA_0,
+ DC_WIN_A_V_INITIAL_DDA_0,
+ DC_WIN_A_DDA_INCREMENT_0,
+ DC_WIN_A_LINE_STRIDE_0,
+ DC_WIN_A_BUF_STRIDE_0,
+ DC_WIN_A_BUFFER_ADDR_MODE_0,
+ DC_WIN_A_DV_CONTROL_0,
+ DC_WIN_A_BLEND_NOKEY_0,
+
+ DC_WINBUF_A_START_ADDR_0 = 0x800,
+ DC_WINBUF_A_START_ADDR_NS_0,
+ DC_WINBUF_A_ADDR_H_OFFSET_0,
+ DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
+ DC_WINBUF_A_ADDR_V_OFFSET_0,
+ DC_WINBUF_A_ADDR_V_OFFSET_NS_0,
+};
+
+#endif
+
git.ucc.asn.au / tpg / acess2.git / commitdiff
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