typedef struct
{
udi_init_context_t init_context;
+
+ struct
+ {
+ udi_index_t pio_index;
+ } init;
- udi_pio_handle_t pio_handle;
+ udi_pio_handle_t pio_handles[1];
udi_ubit8_t macaddr[6];
} ne2k_rdata_t;
(attr)->attr_type = UDI_ATTR_STRING; \
(attr)->attr_length = (len); \
udi_strncpy_rtrim((char *)(attr)->attr_value, (val), (len))
-#define NE2K_SET_ATTR_STRFMT(attr, name, maxlen, fmt, ...) \
+#define NE2K_SET_ATTR_STRFMT(attr, name, maxlen, fmt, v...) \
udi_strcpy((attr)->attr_name, (name)); \
(attr)->attr_type = UDI_ATTR_STRING; \
- (attr)->attr_length = udi_snprintf((char *)(attr)->attr_value, (maxlen), (fmt) ,## __VA_LIST__ )
+ (attr)->attr_length = udi_snprintf((char *)(attr)->attr_value, (maxlen), (fmt) ,## v )
extern udi_channel_event_ind_op_t ne2k_bus_dev_channel_event_ind;
extern udi_bus_bind_ack_op_t ne2k_bus_dev_bus_bind_ack;
+extern udi_pio_map_call_t ne2k_bus_dev_bind__pio_map;
extern udi_bus_unbind_ack_op_t ne2k_bus_dev_bus_unbind_ack;
extern udi_intr_attach_ack_op_t ne2k_bus_dev_intr_attach_ack;
extern udi_intr_detach_ack_op_t ne2k_bus_dev_intr_detach_ack;
PIO_MOV_RI1(R0, 0x40|0x21),
PIO_OUT_RI1(R0, NE2K_REG_CMD),
// CURR = First RX page
- PIO_MOV_RI1(R0, NE2K_FIRST_RX_PAGE),
+ PIO_MOV_RI1(R0, NE2K_RX_FIRST_PG),
PIO_OUT_RI1(R0, NE2K_REG_CURR),
// CMD = 0x21 [Page0, NoDMA, Stop]
PIO_MOV_RI1(R0, 0x21),
// - Read MAC address from EEPROM (24 bytes from 0)
PIO_MOV_RI1(R0, 0),
PIO_MOV_RI1(R1, 0),
- PIO_OUT_RI1(R0, NE2K_REG_RBAR0),
- PIO_OUT_RI1(R1, NE2K_REG_RBAR1),
+ PIO_OUT_RI1(R0, NE2K_REG_RSAR0),
+ PIO_OUT_RI1(R1, NE2K_REG_RSAR1),
PIO_MOV_RI1(R0, 6*4),
PIO_MOV_RI1(R1, 0),
PIO_OUT_RI1(R0, NE2K_REG_RBCR0),
UDI_PIO_REP_ARGS(UDI_PIO_BUF, UDI_PIO_R0, 1, UDI_PIO_R1, 0, UDI_PIO_R2)},
// - Setup
// PSTART = First RX page [Receive area start]
- PIO_MOV_RI1(R0, NE2K_FIRST_RX_PAGE),
+ PIO_MOV_RI1(R0, NE2K_RX_FIRST_PG),
PIO_OUT_RI1(R0, NE2K_REG_PSTART),
// BNRY = Last RX page - 1 [???]
- PIO_MOV_RI1(R0, NE2K_LAST_RX_PAGE-1),
+ PIO_MOV_RI1(R0, NE2K_RX_LAST_PG-1),
PIO_OUT_RI1(R0, NE2K_REG_BNRY),
// PSTOP = Last RX page [???]
- PIO_MOV_RI1(R0, NE2K_LAST_RX_PAGE),
+ PIO_MOV_RI1(R0, NE2K_RX_LAST_PG),
PIO_OUT_RI1(R0, NE2K_REG_PSTOP),
// > Clear all interrupt and set mask
// ISR = 0xFF [ACK all]
udi_ubit16_t list_length;
udi_ubit16_t pio_attributes;
} ne2k_pio_ops[] = {
- {ne2k_pio_reset, ARRAY_SIZEOF(ne2k_pio_reset), 0}}
+ {ne2k_pio_reset, ARRAY_SIZEOF(ne2k_pio_reset), 0}
};
const int NE2K_NUM_PIO_OPS = ARRAY_SIZEOF(ne2k_pio_ops);
// Emit the ND binding
DPT_SET_ATTR32(attr_list, "if_num", 0);
attr_list ++;
- DPT_SET_ATTR_STRING(attr_list, "if_media", "eth");
+ DPT_SET_ATTR_STRING(attr_list, "if_media", "eth", 3);
attr_list ++;
NE2K_SET_ATTR_STRFMT(attr_list, "identifier", 2*6+1, "%2X%2X%2X%2X%2X%2X",
rdata->macaddr[0], rdata->macaddr[1], rdata->macaddr[2],
rdata->macaddr[3], rdata->macaddr[4], rdata->macaddr[5] );
attr_list ++;
udi_enumerate_ack(cb, UDI_ENUMERATE_OK, 2);
- break
+ break;
case UDI_ENUMERATE_NEXT:
udi_enumerate_ack(cb, UDI_ENUMERATE_DONE, 0);
break;
UDI_PCI_BAR_0, 0, 0x20,
ne2k_pio_ops[rdata->init.pio_index].trans_list,
ne2k_pio_ops[rdata->init.pio_index].list_length,
- UDI_PIO_LITTE_ENDIAN, 0, 0
+ UDI_PIO_LITTLE_ENDIAN, 0, 0
);
}
else
ne2k_nd_ctrl_info_req
};
udi_ubit8_t ne2k_nd_ctrl_ops_flags[7] = {0};
-udi_nd_tx_ops ne2k_nd_tx_ops = {
+udi_nd_tx_ops_t ne2k_nd_tx_ops = {
ne2k_nd_tx_channel_event_ind,
ne2k_nd_tx_tx_req,
ne2k_nd_tx_exp_tx_req
};
udi_ubit8_t ne2k_nd_tx_ops_flags[3] = {0};
-udi_nd_rx_ops ne2k_nd_rx_ops = {
+udi_nd_rx_ops_t ne2k_nd_rx_ops = {
ne2k_nd_rx_channel_event_ind,
ne2k_nd_rx_rx_rdy
};
udi_ubit8_t ne2k_nd_rx_ops_flags[2] = {0};
-const udi_primary_init_t ne2k_pri_init = {
+udi_primary_init_t ne2k_pri_init = {
.mgmt_ops = &ne2k_mgmt_ops,
.mgmt_op_flags = ne2k_mgmt_op_flags,
.mgmt_scratch_requirement = 0,
.child_data_size = 0,
.per_parent_paths = 0
};
-const udi_ops_init_t ne2k_ops_list[] = {
+udi_ops_init_t ne2k_ops_list[] = {
{
1, NE2K_META_BUS, UDI_BUS_DEVICE_OPS_NUM,
0,
- (udi_ops_vector_t*)ne2k_bus_dev_ops,
+ (udi_ops_vector_t*)&ne2k_bus_dev_ops,
ne2k_bus_dev_ops_flags
},
{
2, NE2K_META_NIC, UDI_ND_CTRL_OPS_NUM,
0,
- (udi_ops_vector_t*)ne2k_nd_ctrl_ops,
+ (udi_ops_vector_t*)&ne2k_nd_ctrl_ops,
ne2k_nd_ctrl_ops_flags
},
{
3, NE2K_META_NIC, UDI_ND_TX_OPS_NUM,
0,
- (udi_ops_vector_t*)ne2k_nd_tx_ops,
+ (udi_ops_vector_t*)&ne2k_nd_tx_ops,
ne2k_nd_tx_ops_flags
},
{
4, NE2K_META_NIC, UDI_ND_RX_OPS_NUM,
0,
- (udi_ops_vector_t*)ne2k_nd_rx_ops,
+ (udi_ops_vector_t*)&ne2k_nd_rx_ops,
ne2k_nd_rx_ops_flags
},
{0}
-}
+};
const udi_init_t udi_init_info = {
.primary_init_info = &ne2k_pri_init,
.ops_init_list = ne2k_ops_list
* ne2000_hw.h
* - Hardware Definitions
*/
-#ifndef _NE2000_COMMON_H_
-#define _NE2000_COMMON_H_
+#ifndef _NE2000_HW_H_
+#define _NE2000_HW_H_
+
+#define NE2K_MEM_START 0x40
+#define NE2K_MEM_END 0xC0
+#define NE2K_RX_FIRST_PG (NE2K_MEM_START)
+#define NE2K_RX_LAST_PG (NE2K_MEM_START+NE2K_RX_BUF_SIZE-1)
+#define NE2K_RX_BUF_SIZE 0x40
+#define NE2K_TX_FIRST_PG (NE2K_MEM_START+NE2K_RX_BUF_SIZE)
+#define NE2K_TX_LAST_PG (NR2K_MEM_END)
+#define NE2K_TX_BUF_SIZE 0x40
+#define NE2K_MAX_PACKET_QUEUE 10
enum eNe2k_Regs
{
NE2K_REG_CMD,
-}
+ NE2K_REG_CLDA0, //!< Current Local DMA Address 0
+ NE2K_REG_CLDA1, //!< Current Local DMA Address 1
+ NE2K_REG_BNRY, //!< Boundary Pointer (for ringbuffer)
+ NE2K_REG_TSR, //!< Transmit Status Register
+ NE2K_REG_NCR, //!< collisions counter
+ NE2K_REG_FIFO, //!< (for what purpose ??)
+ NE2K_REG_ISR, //!< Interrupt Status Register
+ NE2K_REG_CRDA0, //!< Current Remote DMA Address 0
+ NE2K_REG_CRDA1, //!< Current Remote DMA Address 1
+ // 10: RBCR0
+ // 11: RBCR1
+ NE2K_REG_RSR = 12 //!< Receive Status Register
+};
+
+#define NE2K_REG_PSTART 1 //!< page start (init only)
+#define NE2K_REG_PSTOP 2 //!< page stop (init only)
+// 3: BNRY
+#define NE2K_REG_TPSR 4 //!< transmit page start address
+#define NE2K_REG_TBCR0 5 //!< transmit byte count (low)
+#define NE2K_REG_TBCR1 6 //!< transmit byte count (high)
+// 7: ISR
+#define NE2K_REG_RSAR0 8 //!< remote start address (lo)
+#define NE2K_REG_RSAR1 9 //!< remote start address (hi)
+#define NE2K_REG_RBCR0 10 //!< remote byte count (lo)
+#define NE2K_REG_RBCR1 11 //!< remote byte count (hi)
+#define NE2K_REG_RCR 12 //!< receive config register
+#define NE2K_REG_TCR 13 //!< transmit config register
+#define NE2K_REG_DCR 14 //!< data config register (init)
+#define NE2K_REG_IMR 15 //!< interrupt mask register (init)
+// Page 1
+#define NE2K_REG_CURR 7
+
+// Any page
+#define NE2K_REG_MEM 0x10
+#define NE2K_REG_RESET 0x1F
#endif
git.ucc.asn.au / tpg / acess2.git / commitdiff
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