ARM_CPUNAME = gerneric-armv7
CC = arm-elf-gcc -mcpu=$(ARM_CPUNAME)
-AS = arm-elf-gcc -c
+AS = arm-elf-gcc -mcpu=$(ARM_CPUNAME) -c
LD = arm-elf-ld
OBJDUMP = arm-elf-objdump
DISASM = $(OBJDUMP) -d -S
ARM_CPUNAME = cortex-a9
MODULES += Display/Tegra2Vid
+MODULES += USB/Core USB/EHCI
@echo BUILD_NUM = $$(( $(BUILD_NUM) + 1 )) > Makefile.BuildNum.$(ARCH)
$(POSTBUILD)
@cp $(BIN) $(BIN)_
- @$(STRIP) $(BIN)_
+ @-$(STRIP) $(BIN)_
@gzip -c $(BIN)_ > $(GZBIN)
@$(RM) $(BIN)_
--- /dev/null
+Display CMD Registers
+00000000000000d [Tegra2Vi] 0 - [0x000] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x001] = 0x00000100 (-)
+00000000000000d [Tegra2Vi] 0 - [0x002] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x003] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x004] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x005] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x006] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x007] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x008] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x009] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00A] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00B] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00C] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00D] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00E] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x00F] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x010] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x011] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x012] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x013] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x014] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x015] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x016] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x017] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x018] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x019] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x01A] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x028] = 0x0000011A (-)
+00000000000000d [Tegra2Vi] 0 - [0x029] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02A] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02B] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02C] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02D] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02E] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x02F] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x030] = 0xF000F800 (-)
+00000000000000d [Tegra2Vi] 0 - [0x031] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x032] = 0x00000020 (-)
+00000000000000d [Tegra2Vi] 0 - [0x033] = 0x00000114 (-)
+00000000000000d [Tegra2Vi] 0 - [0x034] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x035] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x036] = 0x00050155 (-)
+00000000000000d [Tegra2Vi] 0 - [0x037] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x038] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x039] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x03A] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x03B] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x03C] = 0x0009060C (-)
+00000000000000d [Tegra2Vi] 0 - [0x03D] = 0x000F021C (-)
+00000000000000d [Tegra2Vi] 0 - [0x03E] = 0x000D0210 (-)
+00000000000000d [Tegra2Vi] 0 - [0x03F] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x040] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x041] = 0x00000000 (DC_CMD_STATE_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x042] = 0x00000010 (DC_CMD_DISPLAY_WINDOW_HEADER_0)
+00000000000000d [Tegra2Vi] 0 - [0x043] = 0x00000000 (DC_CMD_REG_ACT_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - Display COM Registers
+00000000000000d [Tegra2Vi] 0 - [0x300] = 0x00000000 (DC_COM_CRC_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x301] = 0x00000000 (DC_COM_CRC_CHECKSUM_0)
+00000000000000d [Tegra2Vi] 0 - [0x302] = 0x00000000 (DC_COM_PIN_OUTPUT_ENABLE0_0)
+00000000000000d [Tegra2Vi] 0 - [0x303] = 0x00000000 (DC_COM_PIN_OUTPUT_ENABLE1_0)
+00000000000000d [Tegra2Vi] 0 - [0x304] = 0x00000000 (DC_COM_PIN_OUTPUT_ENABLE2_0)
+00000000000000d [Tegra2Vi] 0 - [0x305] = 0x00000000 (DC_COM_PIN_OUTPUT_ENABLE3_0)
+00000000000000d [Tegra2Vi] 0 - [0x306] = 0x00000000 (DC_COM_PIN_OUTPUT_POLARITY0_0)
+00000000000000d [Tegra2Vi] 0 - [0x307] = 0x01000000 (DC_COM_PIN_OUTPUT_POLARITY1_0)
+00000000000000d [Tegra2Vi] 0 - [0x308] = 0x00000000 (DC_COM_PIN_OUTPUT_POLARITY2_0)
+00000000000000d [Tegra2Vi] 0 - [0x309] = 0x00000000 (DC_COM_PIN_OUTPUT_POLARITY3_0)
+00000000000000d [Tegra2Vi] 0 - [0x30A] = 0x00000000 (DC_COM_PIN_OUTPUT_DATA0_0)
+00000000000000d [Tegra2Vi] 0 - [0x30B] = 0x00000000 (DC_COM_PIN_OUTPUT_DATA1_0)
+00000000000000d [Tegra2Vi] 0 - [0x30C] = 0x00000000 (DC_COM_PIN_OUTPUT_DATA2_0)
+00000000000000d [Tegra2Vi] 0 - [0x30D] = 0x00000000 (DC_COM_PIN_OUTPUT_DATA3_0)
+00000000000000d [Tegra2Vi] 0 - [0x30E] = 0x00000000 (DC_COM_PIN_INPUT_ENABLE0_0)
+00000000000000d [Tegra2Vi] 0 - [0x30F] = 0x00000000 (DC_COM_PIN_INPUT_ENABLE1_0)
+00000000000000d [Tegra2Vi] 0 - [0x310] = 0x00000000 (DC_COM_PIN_INPUT_ENABLE2_0)
+00000000000000d [Tegra2Vi] 0 - [0x311] = 0x00000000 (DC_COM_PIN_INPUT_ENABLE3_0)
+00000000000000d [Tegra2Vi] 0 - [0x312] = 0x00000000 (DC_COM_PIN_INPUT_DATA0_0)
+00000000000000d [Tegra2Vi] 0 - [0x313] = 0x00000000 (DC_COM_PIN_INPUT_DATA1_0)
+00000000000000d [Tegra2Vi] 0 - [0x314] = 0x00000000 (DC_COM_PIN_OUTPUT_SELECT0_0)
+00000000000000d [Tegra2Vi] 0 - [0x315] = 0x00000000 (DC_COM_PIN_OUTPUT_SELECT1_0)
+00000000000000d [Tegra2Vi] 0 - [0x316] = 0x00000000 (DC_COM_PIN_OUTPUT_SELECT2_0)
+00000000000000d [Tegra2Vi] 0 - [0x317] = 0x00000000 (DC_COM_PIN_OUTPUT_SELECT3_0)
+00000000000000d [Tegra2Vi] 0 - [0x318] = 0x00210222 (DC_COM_PIN_OUTPUT_SELECT4_0)
+00000000000000d [Tegra2Vi] 0 - [0x319] = 0x00002200 (DC_COM_PIN_OUTPUT_SELECT5_0)
+00000000000000d [Tegra2Vi] 0 - [0x31A] = 0x00020000 (DC_COM_PIN_OUTPUT_SELECT6_0)
+00000000000000d [Tegra2Vi] 0 - [0x31B] = 0x00000000 (DC_COM_PIN_MISC_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x31C] = 0x00840152 (-)
+00000000000000d [Tegra2Vi] 0 - [0x31D] = 0x00000144 (-)
+00000000000000d [Tegra2Vi] 0 - [0x31E] = 0x00700111 (-)
+00000000000000d [Tegra2Vi] 0 - [0x31F] = 0x00000077 (-)
+00000000000000d [Tegra2Vi] 0 - [0x320] = 0x01070023 (-)
+00000000000000d [Tegra2Vi] 0 - [0x321] = 0x0000D317 (-)
+00000000000000d [Tegra2Vi] 0 - [0x322] = 0xEAEE54C2 (-)
+00000000000000d [Tegra2Vi] 0 - [0x323] = 0x6BDC5DA4 (-)
+00000000000000d [Tegra2Vi] 0 - [0x324] = 0x05004210 (-)
+00000000000000d [Tegra2Vi] 0 - [0x325] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x326] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x327] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x328] = 0x00000400 (-)
+00000000000000d [Tegra2Vi] 0 - [0x329] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - Display DISP Registers
+00000000000000d [Tegra2Vi] 0 - [0x400] = 0x00000000 (DC_DISP_DISP_SIGNAL_OPTIONS0_0)
+00000000000000d [Tegra2Vi] 0 - [0x401] = 0x00000000 (DC_DISP_DISP_SIGNAL_OPTIONS1_0)
+00000000000000d [Tegra2Vi] 0 - [0x402] = 0x00000000 (DC_DISP_DISP_WIN_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x403] = 0x00000020 (DC_DISP_MEM_HIGH_PRIORITY_0)
+00000000000000d [Tegra2Vi] 0 - [0x404] = 0x00000001 (DC_DISP_MEM_HIGH_PRIORITY_TIMER_0)
+00000000000000d [Tegra2Vi] 0 - [0x405] = 0x00000000 (DC_DISP_DISP_TIMING_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x406] = 0x0001000B (DC_DISP_REF_TO_SYNC_0)
+00000000000000d [Tegra2Vi] 0 - [0x407] = 0x0004003A (DC_DISP_SYNC_WIDTH_0)
+00000000000000d [Tegra2Vi] 0 - [0x408] = 0x0004003A (DC_DISP_BACK_PORCH_0)
+00000000000000d [Tegra2Vi] 0 - [0x409] = 0x03000400 (DC_DISP_DISP_ACTIVE_0)
+00000000000000d [Tegra2Vi] 0 - [0x40A] = 0x0004003A (DC_DISP_FRONT_PORCH_0)
+00000000000000d [Tegra2Vi] 0 - [0x40B] = 0x00000918 (DC_DISP_H_PULSE0_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x40C] = 0x1D970F55 (DC_DISP_H_PULSE0_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x40D] = 0x02AA0AC5 (DC_DISP_H_PULSE0_POSITION_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x40E] = 0x039B00AA (DC_DISP_H_PULSE0_POSITION_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x40F] = 0x044D1989 (DC_DISP_H_PULSE0_POSITION_D_0)
+00000000000000d [Tegra2Vi] 0 - [0x410] = 0x00000480 (DC_DISP_H_PULSE1_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x411] = 0x198B1E2D (DC_DISP_H_PULSE1_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x412] = 0x04910669 (DC_DISP_H_PULSE1_POSITION_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x413] = 0x08381FA4 (DC_DISP_H_PULSE1_POSITION_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x414] = 0x009C0625 (DC_DISP_H_PULSE1_POSITION_D_0)
+00000000000000d [Tegra2Vi] 0 - [0x415] = 0x00000608 (DC_DISP_H_PULSE2_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x416] = 0x0C001469 (DC_DISP_H_PULSE2_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x417] = 0x07690B17 (DC_DISP_H_PULSE2_POSITION_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x418] = 0x00360257 (DC_DISP_H_PULSE2_POSITION_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x419] = 0x1F1809D6 (DC_DISP_H_PULSE2_POSITION_D_0)
+00000000000000d [Tegra2Vi] 0 - [0x41A] = 0x000007D0 (DC_DISP_V_PULSE0_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x41B] = 0x15CB1886 (DC_DISP_V_PULSE0_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x41C] = 0x02401EA8 (DC_DISP_V_PULSE0_POSITION_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x41D] = 0x09750264 (DC_DISP_V_PULSE0_POSITION_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x41E] = 0x00000010 (DC_DISP_V_PULSE1_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x41F] = 0x16BA0A17 (DC_DISP_V_PULSE1_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x420] = 0x1AE21A90 (DC_DISP_V_PULSE1_POSITION_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x421] = 0x06860AD7 (DC_DISP_V_PULSE1_POSITION_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x422] = 0x00000000 (DC_DISP_V_PULSE2_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x423] = 0x0CC31C03 (DC_DISP_V_PULSE2_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x424] = 0x00000000 (DC_DISP_V_PULSE3_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x425] = 0x07071A0E (DC_DISP_V_PULSE3_POSITION_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x426] = 0x02960DA3 (DC_DISP_M0_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x427] = 0x1F8C1951 (DC_DISP_M1_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x428] = 0x15070003 (DC_DISP_DI_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x429] = 0x0000CEF5 (DC_DISP_PP_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x42A] = 0x10D08381 (DC_DISP_PP_SELECT_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x42B] = 0x1C2CB600 (DC_DISP_PP_SELECT_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x42C] = 0x73B3DE7D (DC_DISP_PP_SELECT_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x42D] = 0x0779CA03 (DC_DISP_PP_SELECT_D_0)
+00000000000000d [Tegra2Vi] 0 - [0x42E] = 0x00000005 (DC_DISP_DISP_CLOCK_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x42F] = 0x00000000 (DC_DISP_DISP_INTERFACE_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x430] = 0x00000200 (DC_DISP_DISP_COLOR_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x431] = 0x00010001 (DC_DISP_SHIFT_CLOCK_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x432] = 0x00000005 (DC_DISP_DATA_ENABLE_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x433] = 0x00000000 (DC_DISP_SERIAL_INTERFACE_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x434] = 0x00000000 (DC_DISP_LCD_SPI_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x435] = 0x00DA0731 (DC_DISP_BORDER_COLOR_0)
+00000000000000d [Tegra2Vi] 0 - [0x436] = 0x00E9B832 (DC_DISP_COLOR_KEY0_LOWER_0)
+00000000000000d [Tegra2Vi] 0 - [0x437] = 0x006B4475 (DC_DISP_COLOR_KEY0_UPPER_0)
+00000000000000d [Tegra2Vi] 0 - [0x438] = 0x000FA6FB (DC_DISP_COLOR_KEY1_LOWER_0)
+00000000000000d [Tegra2Vi] 0 - [0x439] = 0x00304301 (DC_DISP_COLOR_KEY1_UPPER_0)
+00000000000000d [Tegra2Vi] 0 - [0x43A] = 0x00000000 (_DC_DISP_UNUSED_43A)
+00000000000000d [Tegra2Vi] 0 - [0x43B] = 0x00000000 (_DC_DISP_UNUSED_43B)
+00000000000000d [Tegra2Vi] 0 - [0x43C] = 0x004962ED (DC_DISP_CURSOR_FOREGROUND_0)
+00000000000000d [Tegra2Vi] 0 - [0x43D] = 0x0063462E (DC_DISP_CURSOR_BACKGROUND_0)
+00000000000000d [Tegra2Vi] 0 - [0x43E] = 0x3021352C (DC_DISP_CURSOR_START_ADDR_0)
+00000000000000d [Tegra2Vi] 0 - [0x43F] = 0x3021352C (DC_DISP_CURSOR_START_ADDR_NS_0)
+00000000000000d [Tegra2Vi] 0 - [0x440] = 0x21B10B4B (DC_DISP_CURSOR_POSITION_0)
+00000000000000d [Tegra2Vi] 0 - [0x441] = 0x21B10B4B (DC_DISP_CURSOR_POSITION_NS_0)
+00000000000000d [Tegra2Vi] 0 - [0x442] = 0x00000030 (DC_DISP_INIT_SEQ_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x443] = 0x8C0BF46E (DC_DISP_SPI_INIT_SEQ_DATA_A_0)
+00000000000000d [Tegra2Vi] 0 - [0x444] = 0xE08C7EBA (DC_DISP_SPI_INIT_SEQ_DATA_B_0)
+00000000000000d [Tegra2Vi] 0 - [0x445] = 0x89A6A8FD (DC_DISP_SPI_INIT_SEQ_DATA_C_0)
+00000000000000d [Tegra2Vi] 0 - [0x446] = 0x80D5BC36 (DC_DISP_SPI_INIT_SEQ_DATA_D_0)
+00000000000000d [Tegra2Vi] 0 - [0x480] = 0x00000000 (DC_DISP_DC_MCCIF_FIFOCTRL_0)
+00000000000000d [Tegra2Vi] 0 - [0x481] = 0xCF401F1F (DC_DISP_MCCIF_DISPLAY0A_HYST_0)
+00000000000000d [Tegra2Vi] 0 - [0x482] = 0xCF081F1F (DC_DISP_MCCIF_DISPLAY0B_HYST_0)
+00000000000000d [Tegra2Vi] 0 - [0x483] = 0xCF081F1F (DC_DISP_MCCIF_DISPLAY0C_HYST_0)
+00000000000000d [Tegra2Vi] 0 - [0x484] = 0xCF081F1F (DC_DISP_MCCIF_DISPLAY1B_HYST_0)
+00000000000000d [Tegra2Vi] 0 - [0x4C0] = 0x00000000 (DC_DISP_DAC_CRT_CTRL_0)
+00000000000000d [Tegra2Vi] 0 - [0x4C1] = 0x00000002 (DC_DISP_DISP_MISC_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - WINC_A Registers
+00000000000000d [Tegra2Vi] 0 - [0x700] = 0x40000040 (DC_WIN_A_WIN_OPTIONS_0)
+00000000000000d [Tegra2Vi] 0 - [0x701] = 0x00000000 (DC_WIN_A_BYTE_SWAP_0)
+00000000000000d [Tegra2Vi] 0 - [0x702] = 0x00000000 (DC_WIN_A_BUFFER_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x703] = 0x00000006 (DC_WIN_A_COLOR_DEPTH_0)
+00000000000000d [Tegra2Vi] 0 - [0x704] = 0x00000000 (DC_WIN_A_POSITION_0)
+00000000000000d [Tegra2Vi] 0 - [0x705] = 0x03000400 (DC_WIN_A_SIZE_0)
+00000000000000d [Tegra2Vi] 0 - [0x706] = 0x03000800 (DC_WIN_A_PRESCALED_SIZE_0)
+00000000000000d [Tegra2Vi] 0 - [0x707] = 0x00000000 (DC_WIN_A_H_INITIAL_DDA_0)
+00000000000000d [Tegra2Vi] 0 - [0x708] = 0x00000000 (DC_WIN_A_V_INITIAL_DDA_0)
+00000000000000d [Tegra2Vi] 0 - [0x709] = 0x10051004 (DC_WIN_A_DDA_INCREMENT_0)
+00000000000000d [Tegra2Vi] 0 - [0x70A] = 0x00000800 (DC_WIN_A_LINE_STRIDE_0)
+00000000000000d [Tegra2Vi] 0 - [0x70B] = 0x00000000 (DC_WIN_A_BUF_STRIDE_0)
+00000000000000d [Tegra2Vi] 0 - [0x70C] = 0x00000000 (DC_WIN_A_BUFFER_ADDR_MODE_0)
+00000000000000d [Tegra2Vi] 0 - [0x70D] = 0x00000000 (DC_WIN_A_DV_CONTROL_0)
+00000000000000d [Tegra2Vi] 0 - [0x70E] = 0x00000404 (DC_WIN_A_BLEND_NOKEY_0)
+00000000000000d [Tegra2Vi] 0 - [0x70F] = 0x0000FF00 (-)
+00000000000000d [Tegra2Vi] 0 - [0x710] = 0x0000FF00 (-)
+00000000000000d [Tegra2Vi] 0 - [0x711] = 0x00EB0B0D (-)
+00000000000000d [Tegra2Vi] 0 - [0x712] = 0x000C270E (-)
+00000000000000d [Tegra2Vi] 0 - [0x713] = 0x00263E09 (-)
+00000000000000d [Tegra2Vi] 0 - [0x714] = 0x446996C9 (-)
+00000000000000d [Tegra2Vi] 0 - WINBUF_A
+00000000000000d [Tegra2Vi] 0 - [0x800] = 0x1C022000 (DC_WINBUF_A_START_ADDR_0)
+00000000000000d [Tegra2Vi] 0 - [0x801] = 0x1C022000 (DC_WINBUF_A_START_ADDR_NS_0)
+00000000000000d [Tegra2Vi] 0 - [0x802] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x803] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x804] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x805] = 0x00000000 (-)
+00000000000000d [Tegra2Vi] 0 - [0x806] = 0x00000000 (DC_WINBUF_A_ADDR_H_OFFSET_0)
+00000000000000d [Tegra2Vi] 0 - [0x807] = 0x00000000 (DC_WINBUF_A_ADDR_H_OFFSET_NS_0)
+00000000000000d [Tegra2Vi] 0 - [0x808] = 0x00000000 (DC_WINBUF_A_ADDR_V_OFFSET_0)
+00000000000000d [Tegra2Vi] 0 - [0x809] = 0x00000000 (DC_WINBUF_A_ADDR_V_OFFSET_NS_0)
+00000000000000d [Tegra2Vi] 0 - [0x80A] = 0x00000000 (DC_WINBUF_A_UFLOW_STATUS)
* - Driver core
*/
#define DEBUG 0
+#define DUMP_REGISTERS 1
#define VERSION ((0<<8)|10)
#include <acess.h>
#include <errno.h>
tVideo_IOCtl_Pos gTegra2Vid_CursorPos;
// === CODE ===
+inline void _dumpreg(int i)
+{
+ Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x (%s)", i, gpTegra2Vid_IOMem[i],
+ (csaTegra2Vid_RegisterNames[i] ? csaTegra2Vid_RegisterNames[i] : "-"));
+}
/**
*/
int Tegra2Vid_Install(char **Arguments)
// KeyVal_Parse(&gTegra2Vid_KeyValueParser, Arguments);
gpTegra2Vid_IOMem = (void*)MM_MapHWPages(gTegra2Vid_PhysBase, 256/4);
- #if 0
+ #if DUMP_REGISTERS
{
Log_Debug("Tegra2Vid", "Display CMD Registers");
- for( int i = 0x000; i <= 0x01A; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
- for( int i = 0x028; i <= 0x043; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
+ for( int i = 0x000; i <= 0x01A; i ++ ) _dumpreg(i);
+ for( int i = 0x028; i <= 0x043; i ++ ) _dumpreg(i);
Log_Debug("Tegra2Vid", "Display COM Registers");
- for( int i = 0x300; i <= 0x329; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
+ for( int i = 0x300; i <= 0x329; i ++ ) _dumpreg(i);
Log_Debug("Tegra2Vid", "Display DISP Registers");
- for( int i = 0x400; i <= 0x446; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
- for( int i = 0x480; i <= 0x484; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
- for( int i = 0x4C0; i <= 0x4C1; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
-
+ for( int i = 0x400; i <= 0x446; i ++ ) _dumpreg(i);
+ for( int i = 0x480; i <= 0x484; i ++ ) _dumpreg(i);
+ for( int i = 0x4C0; i <= 0x4C1; i ++ ) _dumpreg(i);
Log_Debug("Tegra2Vid", "WINC_A Registers");
- for( int i = 0x700; i <= 0x714; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
+ for( int i = 0x700; i <= 0x714; i ++ ) _dumpreg(i);
Log_Debug("Tegra2Vid", "WINBUF_A");
- for( int i = 0x800; i <= 0x80A; i ++ )
- Log_Debug("Tegra2Vid", "[0x%03x] = 0x%08x", i, gpTegra2Vid_IOMem[i]);
+ for( int i = 0x800; i <= 0x80A; i ++ ) _dumpreg(i);
}
#endif
-// return 1;
// HACK!!!
#if 0
);
memset(gpTegra2Vid_Framebuffer, 0xFF, 0x1000);
-// gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] &= ~0x40;
+#if 0
+ gpTegra2Vid_IOMem[DC_WIN_A_WIN_OPTIONS_0] = (1 << 30);
gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB)
+ gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0];
+ gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] =
+ gTegra2Vid_DrvUtil_BufInfo.Pitch =
+ 1680*4;
+ gTegra2Vid_DrvUtil_BufInfo.Depth = 32;
+ gTegra2Vid_DrvUtil_BufInfo.Width = 1680;
+ gTegra2Vid_DrvUtil_BufInfo.Height = 1050;
+#else
+ gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 13; // Could be 13 (BGR/RGB)
+ gpTegra2Vid_IOMem[DC_WIN_A_LINE_STRIDE_0] =
+ gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4;
+ gTegra2Vid_DrvUtil_BufInfo.Depth = 32;
gTegra2Vid_DrvUtil_BufInfo.Width = 1024;
gTegra2Vid_DrvUtil_BufInfo.Height = 768;
- gTegra2Vid_DrvUtil_BufInfo.Pitch = 1024*4;
- gTegra2Vid_DrvUtil_BufInfo.Depth = 32;
gTegra2Vid_DrvUtil_BufInfo.Framebuffer = gpTegra2Vid_Framebuffer;
+#endif
+ gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ;
// Tegra2Vid_int_SetMode(4);
{
const struct sTegra2_Disp_Mode *mode = &caTegra2Vid_Modes[Mode];
int w = mode->W, h = mode->H; // Horizontal/Vertical Active
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_FRONT_PORCH_0) = (mode->VFP << 16) | mode->HFP;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_SYNC_WIDTH_0) = (mode->HS << 16) | mode->HS;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_BACK_PORCH_0) = (mode->VBP << 16) | mode->HBP;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_ACTIVE_0) = (mode->H << 16) | mode->W;
-
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_POSITION_0) = 0;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_SIZE_0) = (h << 16) | w;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_DISP_DISP_COLOR_CONTROL_0) = 0x8; // BASE888
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_COLOR_DEPTH_0) = 12; // Could be 13 (BGR/RGB)
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WIN_A_PRESCALED_SIZE_0) = (h << 16) | w;
+ gpTegra2Vid_IOMem[DC_DISP_FRONT_PORCH_0] = (mode->VFP << 16) | mode->HFP;
+ gpTegra2Vid_IOMem[DC_DISP_SYNC_WIDTH_0] = (mode->HS << 16) | mode->HS;
+ gpTegra2Vid_IOMem[DC_DISP_BACK_PORCH_0] = (mode->VBP << 16) | mode->HBP;
+ gpTegra2Vid_IOMem[DC_DISP_DISP_ACTIVE_0] = (mode->H << 16) | mode->W;
+
+ gpTegra2Vid_IOMem[DC_WIN_A_POSITION_0] = 0;
+ gpTegra2Vid_IOMem[DC_WIN_A_SIZE_0] = (h << 16) | w;
+ gpTegra2Vid_IOMem[DC_DISP_DISP_COLOR_CONTROL_0] = 0x8; // BASE888
+ gpTegra2Vid_IOMem[DC_WIN_A_COLOR_DEPTH_0] = 12; // Could be 13 (BGR/RGB)
+ gpTegra2Vid_IOMem[DC_WIN_A_PRESCALED_SIZE_0] = (h << 16) | w;
Log_Debug("Tegra2Vid", "Mode %i (%ix%i) selected", Mode, w, h);
giTegra2Vid_FramebufferSize = w*h*4;
+ // TODO: Does this need RAM or unmapped space?
gpTegra2Vid_Framebuffer = (void*)MM_AllocDMA(
(giTegra2Vid_FramebufferSize + PAGE_SIZE-1) / PAGE_SIZE,
32,
);
// Tell hardware
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_START_ADDR_0) = gTegra2Vid_FramebufferPhys;
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_V_OFFSET_0) = 0; // Y offset
- *(Uint32*)(gpTegra2Vid_IOMem + DC_WINBUF_A_ADDR_H_OFFSET_0) = 0; // X offset
+ gpTegra2Vid_IOMem[DC_WINBUF_A_START_ADDR_0] = gTegra2Vid_FramebufferPhys;
+ gpTegra2Vid_IOMem[DC_WINBUF_A_ADDR_V_OFFSET_0] = 0; // Y offset
+ gpTegra2Vid_IOMem[DC_WINBUF_A_ADDR_H_OFFSET_0] = 0; // X offset
}
+ gpTegra2Vid_IOMem[DC_CMD_STATE_CONTROL_0] = WIN_A_ACT_REQ;
+
return 0;
}
Uint16 HBP, VBP;
} caTegra2Vid_Modes[] = {
// TODO: VESA timings
-// {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
-// {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
-// {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
-// {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
-// {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
+ {1024, 768, 58, 4, 58, 4, 58, 4}, // 1024x768 (reset), RtS=11,4
+ // TV Timings
+ {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
+ {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
+ {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
+ {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
+ {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
// TODO: Can all but HA/VA be constant and those select the resolution?
};
const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
DC_WIN_A_BUFFER_ADDR_MODE_0,
DC_WIN_A_DV_CONTROL_0,
DC_WIN_A_BLEND_NOKEY_0,
+ DC_WIN_A_BLEND_1WIN_0,
+ DC_WIN_A_BLEND_2WIN_B_0,
+ DC_WIN_A_BLEND_2WIN_C_0,
+ DC_WIN_A_BLEND_3WIN_BC_0,
+ DC_WIN_A_HP_FETCH_CONTROL_0,
+
DC_WINBUF_A_START_ADDR_0 = 0x800,
DC_WINBUF_A_START_ADDR_NS_0,
DC_WINBUF_A_ADDR_V_OFFSET_NS_0,
};
+#if DEBUG || DUMP_REGISTERS
+const char * const csaTegra2Vid_RegisterNames[] = {
+ [0x000] = "DC_CMD_GENERAL_INCR_SYNCPT_0",
+ "DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0",
+ "DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0",
+ [0x008] = "DC_CMD_WIN_A_INCR_SYNCPT_0",
+ "DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0",
+ "DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0",
+ [0x010] = "DC_CMD_WIN_B_INCR_SYNCPT_0",
+ "DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0",
+ "DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0",
+ [0x018] = "DC_CMD_WIN_C_INCR_SYNCPT_0",
+ "DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0",
+ "DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0",
+ [0x028] = "DC_CMD_CONT_SYNCPT_VSYNC_0",
+ [0x030] = "DC_CMD_CTXSW_0",
+ "DC_CMD_DISPLAY_COMMAND_OPTION0_0",
+ "DC_CMD_DISPLAY_COMMAND_0",
+ "DC_CMD_SIGNAL_RAISE_0",
+ [0x036] = "DC_CMD_DISPLAY_POWER_CONTROL_0",
+ "DC_CMD_INT_STATUS_0",
+ "DC_CMD_INT_MASK_0",
+ "DC_CMD_INT_ENABLE_0",
+ "DC_CMD_INT_TYPE_0",
+ "DC_CMD_INT_POLARITY_0",
+ "DC_CMD_SIGNAL_RAISE1_0",
+ "DC_CMD_SIGNAL_RAISE2_0",
+ "DC_CMD_SIGNAL_RAISE3_0",
+
+ [0x040] = "DC_CMD_STATE_ACCESS_0",
+ "DC_CMD_STATE_CONTROL_0",
+ "DC_CMD_DISPLAY_WINDOW_HEADER_0", // 042
+ "DC_CMD_REG_ACT_CONTROL_0", // 043
+
+ [0x300] = "DC_COM_CRC_CONTROL_0",
+ "DC_COM_CRC_CHECKSUM_0", // 301
+ "DC_COM_PIN_OUTPUT_ENABLE0_0", // 302
+ "DC_COM_PIN_OUTPUT_ENABLE1_0", // 303
+ "DC_COM_PIN_OUTPUT_ENABLE2_0", // 304
+ "DC_COM_PIN_OUTPUT_ENABLE3_0", // 305
+ "DC_COM_PIN_OUTPUT_POLARITY0_0", // 306
+ "DC_COM_PIN_OUTPUT_POLARITY1_0", // 307
+ "DC_COM_PIN_OUTPUT_POLARITY2_0", // 308
+ "DC_COM_PIN_OUTPUT_POLARITY3_0", // 309
+ "DC_COM_PIN_OUTPUT_DATA0_0", // 30A
+ "DC_COM_PIN_OUTPUT_DATA1_0", // 30B
+ "DC_COM_PIN_OUTPUT_DATA2_0", // 30C
+ "DC_COM_PIN_OUTPUT_DATA3_0", // 30D
+ "DC_COM_PIN_INPUT_ENABLE0_0", // 30E
+ "DC_COM_PIN_INPUT_ENABLE1_0", // 30F
+ "DC_COM_PIN_INPUT_ENABLE2_0", // 310
+ "DC_COM_PIN_INPUT_ENABLE3_0", // 311
+ "DC_COM_PIN_INPUT_DATA0_0", // 312
+ "DC_COM_PIN_INPUT_DATA1_0", // 313
+ "DC_COM_PIN_OUTPUT_SELECT0_0", // 314
+ "DC_COM_PIN_OUTPUT_SELECT1_0", // 315
+ "DC_COM_PIN_OUTPUT_SELECT2_0", // 316
+ "DC_COM_PIN_OUTPUT_SELECT3_0", // 317
+ "DC_COM_PIN_OUTPUT_SELECT4_0", // 318
+ "DC_COM_PIN_OUTPUT_SELECT5_0", // 319
+ "DC_COM_PIN_OUTPUT_SELECT6_0", // 31A
+ "DC_COM_PIN_MISC_CONTROL_0", // 31B
+ // TODO: Complete
+
+ [0x400] = "DC_DISP_DISP_SIGNAL_OPTIONS0_0",
+ "DC_DISP_DISP_SIGNAL_OPTIONS1_0", // 401
+ "DC_DISP_DISP_WIN_OPTIONS_0", // 402
+ "DC_DISP_MEM_HIGH_PRIORITY_0", // 403
+ "DC_DISP_MEM_HIGH_PRIORITY_TIMER_0", // 404
+ "DC_DISP_DISP_TIMING_OPTIONS_0", // 405
+ "DC_DISP_REF_TO_SYNC_0", // 406 (TrimSlice 0x0001 000B)
+ "DC_DISP_SYNC_WIDTH_0", // 407 (TrimSlice 0x0004 003A)
+ "DC_DISP_BACK_PORCH_0", // 408 (TrimSlice 0x0004 003A)
+ "DC_DISP_DISP_ACTIVE_0", // 409 (TrimSlice 0x0300 0400)
+ "DC_DISP_FRONT_PORCH_0", // 40A (TrimSlice 0x0004 003A)
+ "DC_DISP_H_PULSE0_CONTROL_0", // 40B
+ "DC_DISP_H_PULSE0_POSITION_A_0", // 40C
+ "DC_DISP_H_PULSE0_POSITION_B_0", // 40D
+ "DC_DISP_H_PULSE0_POSITION_C_0", // 40E
+ "DC_DISP_H_PULSE0_POSITION_D_0", // 40F
+ "DC_DISP_H_PULSE1_CONTROL_0", // 410
+ "DC_DISP_H_PULSE1_POSITION_A_0", // 411
+ "DC_DISP_H_PULSE1_POSITION_B_0", // 412
+ "DC_DISP_H_PULSE1_POSITION_C_0", // 413
+ "DC_DISP_H_PULSE1_POSITION_D_0", // 414
+ "DC_DISP_H_PULSE2_CONTROL_0", // 415
+ "DC_DISP_H_PULSE2_POSITION_A_0", // 416
+ "DC_DISP_H_PULSE2_POSITION_B_0", // 417
+ "DC_DISP_H_PULSE2_POSITION_C_0", // 418
+ "DC_DISP_H_PULSE2_POSITION_D_0", // 419
+ "DC_DISP_V_PULSE0_CONTROL_0", // 41A
+ "DC_DISP_V_PULSE0_POSITION_A_0", // 41B
+ "DC_DISP_V_PULSE0_POSITION_B_0", // 41C
+ "DC_DISP_V_PULSE0_POSITION_C_0", // 41D
+ "DC_DISP_V_PULSE1_CONTROL_0", // 41E
+ "DC_DISP_V_PULSE1_POSITION_A_0", // 41F
+ "DC_DISP_V_PULSE1_POSITION_B_0", // 420
+ "DC_DISP_V_PULSE1_POSITION_C_0", // 421
+ "DC_DISP_V_PULSE2_CONTROL_0", // 422
+ "DC_DISP_V_PULSE2_POSITION_A_0", // 423
+ "DC_DISP_V_PULSE3_CONTROL_0", // 424
+ "DC_DISP_V_PULSE3_POSITION_A_0", // 425
+ "DC_DISP_M0_CONTROL_0", // 426
+ "DC_DISP_M1_CONTROL_0", // 427
+ "DC_DISP_DI_CONTROL_0", // 428
+ "DC_DISP_PP_CONTROL_0", // 429
+ "DC_DISP_PP_SELECT_A_0", // 42A
+ "DC_DISP_PP_SELECT_B_0", // 42B
+ "DC_DISP_PP_SELECT_C_0", // 42C
+ "DC_DISP_PP_SELECT_D_0", // 42D
+ "DC_DISP_DISP_CLOCK_CONTROL_0", // 42E
+ "DC_DISP_DISP_INTERFACE_CONTROL_0",//42F
+ "DC_DISP_DISP_COLOR_CONTROL_0", // 430
+ "DC_DISP_SHIFT_CLOCK_OPTIONS_0", // 431
+ "DC_DISP_DATA_ENABLE_OPTIONS_0", // 432
+ "DC_DISP_SERIAL_INTERFACE_OPTIONS_0", // 433
+ "DC_DISP_LCD_SPI_OPTIONS_0", // 434
+ "DC_DISP_BORDER_COLOR_0", // 435
+ "DC_DISP_COLOR_KEY0_LOWER_0", // 436
+ "DC_DISP_COLOR_KEY0_UPPER_0", // 437
+ "DC_DISP_COLOR_KEY1_LOWER_0", // 438
+ "DC_DISP_COLOR_KEY1_UPPER_0", // 439
+ "_DC_DISP_UNUSED_43A",
+ "_DC_DISP_UNUSED_43B",
+ "DC_DISP_CURSOR_FOREGROUND_0", // 43C - IMPORTANT
+ "DC_DISP_CURSOR_BACKGROUND_0", // 43D - IMPORTANT
+ "DC_DISP_CURSOR_START_ADDR_0", // 43E - IMPORTANT
+ "DC_DISP_CURSOR_START_ADDR_NS_0", // 43F - IMPORTANT
+ "DC_DISP_CURSOR_POSITION_0", // 440 - IMPORTANT
+ "DC_DISP_CURSOR_POSITION_NS_0", // 441 - IMPORTANT
+ "DC_DISP_INIT_SEQ_CONTROL_0", // 442
+ "DC_DISP_SPI_INIT_SEQ_DATA_A_0", // 443
+ "DC_DISP_SPI_INIT_SEQ_DATA_B_0", // 444
+ "DC_DISP_SPI_INIT_SEQ_DATA_C_0", // 445
+ "DC_DISP_SPI_INIT_SEQ_DATA_D_0", // 446
+
+ [0x480] = "DC_DISP_DC_MCCIF_FIFOCTRL_0",
+ "DC_DISP_MCCIF_DISPLAY0A_HYST_0", // 481
+ "DC_DISP_MCCIF_DISPLAY0B_HYST_0", // 482
+ "DC_DISP_MCCIF_DISPLAY0C_HYST_0", // 483
+ "DC_DISP_MCCIF_DISPLAY1B_HYST_0", // 484
+
+ [0x4C0] = "DC_DISP_DAC_CRT_CTRL_0",
+ "DC_DISP_DISP_MISC_CONTROL_0", // 4C1
+
+ [0x500] = "DC_WINC_A_COLOR_PALETTE_0",
+ [0x600] = "DC_WINC_A_PALETTE_COLOR_EXT_0",
+ [0x700] = "DC_WIN_A_WIN_OPTIONS_0",
+ "DC_WIN_A_BYTE_SWAP_0", // 701
+ "DC_WIN_A_BUFFER_CONTROL_0", // 702
+ "DC_WIN_A_COLOR_DEPTH_0", // 703
+ "DC_WIN_A_POSITION_0", // 704
+ "DC_WIN_A_SIZE_0", // 705 (TrimSlice 0x0300 0400)
+ "DC_WIN_A_PRESCALED_SIZE_0",
+ "DC_WIN_A_H_INITIAL_DDA_0",
+ "DC_WIN_A_V_INITIAL_DDA_0",
+ "DC_WIN_A_DDA_INCREMENT_0",
+ "DC_WIN_A_LINE_STRIDE_0",
+ "DC_WIN_A_BUF_STRIDE_0",
+ "DC_WIN_A_BUFFER_ADDR_MODE_0",
+ "DC_WIN_A_DV_CONTROL_0",
+ "DC_WIN_A_BLEND_NOKEY_0",
+ "DC_WIN_A_BLEND_1WIN_0",
+ "DC_WIN_A_BLEND_2WIN_B_0",
+ "DC_WIN_A_BLEND_2WIN_C_0",
+ "DC_WIN_A_BLEND_3WIN_BC_0",
+ "DC_WIN_A_HP_FETCH_CONTROL_0",
+
+ [0x800] = "DC_WINBUF_A_START_ADDR_0",
+ [0x801] = "DC_WINBUF_A_START_ADDR_NS_0",
+ [0x806] = "DC_WINBUF_A_ADDR_H_OFFSET_0",
+ [0x807] = "DC_WINBUF_A_ADDR_H_OFFSET_NS_0",
+ [0x808] = "DC_WINBUF_A_ADDR_V_OFFSET_0",
+ [0x809] = "DC_WINBUF_A_ADDR_V_OFFSET_NS_0",
+ [0x80A] = "DC_WINBUF_A_UFLOW_STATUS"
+};
+#endif
+
+// Bit definitions
+/// \name DC_CMD_STATE_CONTROL_0
+/// \{
+#define GEN_ACT_REQ 0x0001
+#define WIN_A_ACT_REQ 0x0002
+#define WIN_B_ACT_REQ 0x0004
+#define WIN_C_ACT_REQ 0x0008
+/// \}
+
#endif
int HFP, HSync, HDisplay, HBP;
int VFP, VSync, VDisplay, VBP;
} csaTimings[] = {
- {40, 128, 800, 88, 1, 4, 600, 23}, // SVGA @ 60Hz
- {24, 136, 1024, 160, 3, 6, 768, 29}, // XGA @ 60Hz
+ {40, 128, 800, 88, 1, 4, 600, 23}, // SVGA @ 60Hz
+ {24, 136, 1024, 160, 3, 6, 768, 29}, // XGA @ 60Hz
{38, 112, 1280, 248, 1, 3, 1024, 38} // 1280x1024 @ 60Hz
};
const Uint16 caVIAVideo_CardIDs[][2] = {
// === PROTOTYPES ===
int RAMFS_Install(char **Arguments);
-void RAMFS_Cleanup(void);
+ int RAMFS_Cleanup(void);
// --- Mount/Unmount ---
tVFS_Node *RAMFS_InitDevice(const char *Device, const char **Options);
void RAMFS_Unmount(tVFS_Node *Node);
return 0;
}
-void RAMFS_Cleanup(void)
+int RAMFS_Cleanup(void)
{
-
+ return 0;
}
--- /dev/null
+#
+# Acess2 EHCI Driver
+#
+
+OBJ = ehci.o
+CPPFLAGS = -I../Core/include
+NAME = EHCI
+
+-include ../Makefile.tpl
--- /dev/null
+/*
+ * Acess2 EHCI Driver
+ * - By John Hodge (thePowersGang)
+ *
+ * ehci.c
+ * - Driver Core
+ */
+#define DEBUG 1
+#define VERSION VER2(0,1)
+#include <acess.h>
+#include <modules.h>
+#include <usb_host.h>
+#include "ehci.h"
+#include <drv_pci.h>
+
+// === CONSTANTS ===
+#define EHCI_MAX_CONTROLLERS 4
+
+// === PROTOTYPES ===
+ int EHCI_Initialise(char **Arguments);
+ int EHCI_Cleanup(void);
+ int EHCI_InitController(tPAddr BaseAddress, Uint8 InterruptNum);
+void EHCI_InterruptHandler(int IRQ, void *Ptr);
+// -- API ---
+void *EHCI_InitInterrupt(void *Ptr, int Endpoint, int bInput, int Period, tUSBHostCb Cb, void *CbData, void *Buf, size_t Length);
+void *EHCI_InitIsoch (void *Ptr, int Endpoint);
+void *EHCI_InitControl(void *Ptr, int Endpoint);
+void *EHCI_InitBulk (void *Ptr, int Endpoint);
+void *EHCI_RemEndpoint(void *Ptr, void *Handle);
+void *EHCI_SETUP(void *Ptr, void *Dest, tUSBHostCb Cb, void *CbData, void *Data, size_t Length);
+void *EHCI_IN (void *Ptr, void *Dest, tUSBHostCb Cb, void *CbData, void *Data, size_t Length);
+void *EHCI_OUT (void *Ptr, void *Dest, tUSBHostCb Cb, void *CbData, void *Data, size_t Length);
+
+// === GLOBALS ===
+MODULE_DEFINE(0, VERSION, USB_EHCI, EHCI_Initialise, NULL, "USB_Core", NULL);
+tEHCI_Controller gaEHCI_Controllers[EHCI_MAX_CONTROLLERS];
+
+// === CODE ===
+int EHCI_Initialise(char **Arguments)
+{
+ for( int id = -1; (id = PCI_GetDeviceByClass(0x0C0320, 0xFFFFFF, id)) >= 0; )
+ {
+ Uint32 addr = PCI_GetBAR(id, 0);
+ if( addr == 0 ) {
+ // Oops, PCI BIOS emulation time
+ }
+ Uint8 irq = PCI_GetIRQ(id);
+ if( irq == 0 ) {
+ // TODO: The same
+ }
+
+ if( EHCI_InitController(addr, irq) ) {
+ // TODO: Detect other forms of failure than "out of slots"
+ break ;
+ }
+ }
+ return 0;
+}
+
+int EHCI_Cleanup(void)
+{
+ return 0;
+}
+
+// --- Driver Init ---
+int EHCI_InitController(tPAddr BaseAddress, Uint8 InterruptNum)
+{
+ tEHCI_Controller *cont = NULL;
+
+ for( int i = 0; i < EHCI_MAX_CONTROLLERS; i ++ )
+ {
+ if( gaEHCI_Controllers[i].PhysBase == 0 ) {
+ cont = &gaEHCI_Controllers[i];
+ cont->PhysBase = BaseAddress;
+ break;
+ }
+ }
+
+ if(!cont) {
+ return 1;
+ }
+
+ // -- Build up structure --
+ cont->CapRegs = (void*)MM_MapHWPages(BaseAddress, 1);
+ // TODO: Error check
+ cont->OpRegs = (void*)( (Uint32*)cont->CapRegs + cont->CapRegs->CapLength / 4 );
+ // - Allocate periodic queue
+ cont->PeriodicQueue = (void*)MM_AllocDMA(1, 32, NULL);
+ // TODO: Error check
+
+ // -- Bind IRQ --
+ IRQ_AddHandler(InterruptNum, EHCI_InterruptHandler, cont);
+
+ // -- Initialisation procedure (from ehci-r10) --
+ // - Reset controller
+ cont->OpRegs->USBCmd = USBCMD_HCReset;
+ // - Set CTRLDSSEGMENT (TODO: 64-bit support)
+ // - Set USBINTR
+ cont->OpRegs->USBIntr = USBINTR_IOC|USBINTR_PortChange|USBINTR_FrameRollover;
+ // - Set PERIODICLIST BASE
+ cont->OpRegs->PeridocListBase = MM_GetPhysAddr( (tVAddr) cont->PeriodicQueue );
+ // - Enable controller
+ cont->OpRegs->USBCmd = (0x40 << 16) | USBCMD_PeriodicEnable | USBCMD_Run;
+ // - Route all ports
+ cont->OpRegs->ConfigFlag = 1;
+
+ return 0;
+}
+
+void EHCI_InterruptHandler(int IRQ, void *Ptr)
+{
+
+}
#ifndef _EHCI_H_
#define _EHCI_H_
+typedef struct sEHCI_CapRegs tEHCI_CapRegs;
+typedef struct sEHCI_OpRegs tEHCI_OpRegs;
+typedef struct sEHCI_iTD tEHCI_iTD;
+typedef struct sEHCI_siTD tEHCI_siTD;
+typedef struct sEHCI_qTD tEHCI_qTD;
+typedef struct sEHCI_QH tEHCI_QH;
+typedef struct sEHCI_Controller tEHCI_Controller;
+
struct sEHCI_CapRegs
{
Uint8 CapLength; // Byte offset of Operational registers
Uint32 PortSC[15];
};
+#define USBCMD_Run 0x0001
+#define USBCMD_HCReset 0x0002
+#define USBCMD_PeriodicEnable 0x0010
+#define USBCMD_AsyncEnable 0x0020
+
+#define USBINTR_IOC 0x0001
+#define USBINTR_Error 0x0002
+#define USBINTR_PortChange 0x0004
+#define USBINTR_FrameRollover 0x0008
+#define USBINTR_HostSystemError 0x0010
+#define USBINTR_AsyncAdvance 0x0020
+
+struct sEHCI_iTD
+{
+ Uint32 Link;
+ struct {
+ Uint16 Offset;
+ Uint16 LengthSts;
+ } Transactions[8];
+ // -- 0 --
+ // 0:6 - Device
+ // 7 - Reserved
+ // 8:11 - Endpoint
+ // -- 1 --
+ // 0:10 - Max packet size
+ // 11 - IN/OUT
+ Uint32 BufferPointers[8]; // Page aligned, low 12 bits are overloaded
+};
+
+struct sEHCI_siTD
+{
+ Uint32 Link;
+ Uint32 Dest;
+ Uint32 uFrame;
+ Uint32 StatusLength;
+ Uint32 Page0;
+ Uint32 Page1;
+ Uint32 BackLink;
+};
+
+struct sEHCI_qTD
+{
+ Uint32 Link;
+ Uint32 Link2; // Used when there's a short packet
+ Uint32 Token;
+ Uint32 Pages[5]; //First has offset in low 12 bits
+};
+
+struct sEHCI_QH
+{
+ Uint32 HLink; // Horizontal link
+ Uint32 Endpoint;
+ Uint32 EndpointExt;
+ Uint32 CurrentTD;
+ tEHCI_qTD Overlay;
+};
+
+struct sEHCI_Controller
+{
+ tPAddr PhysBase;
+ tEHCI_CapRegs *CapRegs;
+ tEHCI_OpRegs *OpRegs;
+
+ Uint32 *PeriodicQueue;
+};
+
#endif
DRIVERS :=
MODULES :=
+MODULES += Filesystems/RAMDisk
MODULES += Filesystems/Ext2
MODULES += Filesystems/FAT
MODULES += Filesystems/NTFS
git.ucc.asn.au / tpg / acess2.git / commitdiff
UCC git Repository :: git.ucc.asn.au