+\section{On the design of fast IEEE floating-point adders\cite{seidel2001onthe}}
+
+This paper gives an overview of the ``Naive'' floating point addition/subtraction algorithm and gives several optimisation techniques:
+
+TODO: Actually understand these...
+
+\begin{itemize}
+ \item Use parallel paths (based on exponent)
+ \item Unification of significand result ranges
+ \item Reduction of IEEE rounding modes
+ \item Sign-magnitude computation of a difference
+ \item Compound Addition
+ \item Approximate counting of leading zeroes
+ \item Pre-computation of post-normalization shift
+\end{itemize}
+
+They then give an implementation that uses these optimisation techniques including very scary looking block diagrams.
+
+They simulated the FPU. Does not mention what simulation method was used directly, but cites another paper (TODO: Look at this. I bet it was VHDL).
+
+The paper concludes by summarising the optimisation techniques used by various adders in production (in 2001).
+
+This paper does not specifically mention the precision of the operations, but may be useful because a faster adder design might mean you can increase the precision.
+