Don't print random debug information

[ipdf/vfpu.git] / src / main.vhd

diff --git a/src/main.vhd b/src/main.vhd
index 99596ee..36bc8fc 100644 (file)
--- a/src/main.vhd
+++ b/src/main.vhd
@@ -10,6 +10,8 @@ use ieee.std_logic_misc.all;
 use std.textio.all;
 use work.txt_util.all;
 
+use work.fpupack.all;
+
         -- fpu operations (fpu_op_i):
                -- ========================
                -- 000 = add, 
@@ -55,18 +57,26 @@ component fpu
        );   
 end component;
 
-
+-- Assigning default values doesn't seem to help the error messages :(
 signal clk_i : std_logic:= '1';
-signal opa_i, opb_i : std_logic_vector(31 downto 0) := (others => '0');
+signal opa_i, opb_i : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
 signal fpu_op_i                : std_logic_vector(2 downto 0) := (others => '0');
 signal rmode_i : std_logic_vector(1 downto 0) := (others => '0');
-signal output_o : std_logic_vector(31 downto 0) := (others => '0');
-signal start_i, ready_o : std_logic := '0';
-signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic := '0';
+signal output_o : std_logic_vector(FP_WIDTH-1 downto 0) := (others => '0');
+signal start_i : std_logic := '1';
+signal ready_o : std_logic := '1';
+signal ine_o : std_logic := '0';
+signal overflow_o : std_logic := '0';
+signal underflow_o : std_logic := '0';
+signal div_zero_o : std_logic := '0';
+signal inf_o : std_logic := '0';
+signal zero_o : std_logic := '0';
+signal qnan_o : std_logic := '0';
+signal snan_o : std_logic := '0';
 
 
 
-signal slv_out : std_logic_vector(31 downto 0);
+signal slv_out : std_logic_vector(FP_WIDTH-1 downto 0);
 
 constant CLK_PERIOD :time := 10 ns; -- period of clk period
 
@@ -104,7 +114,7 @@ begin
                file input_file: TEXT open read_mode is "STD_INPUT"; 
 
                variable file_line: line;
-               variable str_in: string(8 downto 1);
+               variable str_in: string(FP_WIDTH/4 downto 1);
                variable str_fpu_op: string(3 downto 1);
                variable str_rmode: string(2 downto 1);
 
@@ -112,32 +122,41 @@ begin
 
     begin
                -- Read ops from input_file
+               --print(str(ZERO_VECTOR));
+               --print(str(INF));
+               --print(str(QNAN));
+               --print(str(SNAN));
                start_i <= '0';
                while not endfile(input_file) loop
 
                        wait for CLK_PERIOD; 
                        start_i <= '1';
                        
-                       str_read(input,str_in);
+                       str_read(input_file,str_in);
                        opa_i <= strhex_to_slv(str_in);
                        
-                       str_read(input,str_in);
+                       str_read(input_file,str_in);
                        opb_i <= strhex_to_slv(str_in);
 
                        str_read(input_file,str_fpu_op);
-                       fpu_op_i <= to_std_logic_vector(str_fpu_op);
+                       fpu_op_i <= strhex_to_slv(str_fpu_op)(2 downto 0);
                        
                        str_read(input_file,str_rmode);
-                       rmode_i <= to_std_logic_vector(str_rmode);
-                       
-                       str_read(input_file,str_in);
-                       slv_out <= strhex_to_slv(str_in);
+                       rmode_i <= strhex_to_slv(str_rmode)(1 downto 0);
+
+
 
                        wait for CLK_PERIOD;
                        start_i <= '0'; 
                        wait until ready_o='1';
                        
+                       --print("OpA"); print(hstr(opa_i));
+                       --print("OpB"); print(hstr(opb_i));
+                       --print("Opcode"); print(hstr(fpu_op_i));
+                       --print("Rmode"); print(hstr(rmode_i));
                        
+
+
                        print(hstr(output_o));
                        
                end loop;