2 * Acess2 NVidia Tegra2 Display Driver
3 * - By John Hodge (thePowersGang)
8 #ifndef _TEGRA2_DISP_H_
9 #define _TEGRA2_DISP_H_
11 #define TEGRA2VID_BASE 0x54200000 // 0x40000 Large (256 KB)
13 const struct sTegra2_Disp_Mode
19 } caTegra2Vid_Modes[] = {
21 {1024, 768, 58, 4, 58, 4, 58, 4}, // 1024x768 (reset), RtS=11,4
23 {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
24 {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
25 {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
26 {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
27 {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
28 // TODO: Can all but HA/VA be constant and those select the resolution?
30 const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
32 enum eTegra2_Disp_Regs
34 DC_CMD_STATE_CONTROL_0 = 0x041,
35 DC_CMD_DISPLAY_WINDOW_HEADER_0, // 042
36 DC_CMD_REG_ACT_CONTROL_0, // 043
38 DC_COM_CRC_CONTROL_0 = 0x300,
39 DC_COM_CRC_CHECKSUM_0, // 301
40 DC_COM_PIN_OUTPUT_ENABLE0_0, // 302
41 DC_COM_PIN_OUTPUT_ENABLE1_0, // 303
42 DC_COM_PIN_OUTPUT_ENABLE2_0, // 304
43 DC_COM_PIN_OUTPUT_ENABLE3_0, // 305
44 DC_COM_PIN_OUTPUT_POLARITY0_0, // 306
45 DC_COM_PIN_OUTPUT_POLARITY1_0, // 307
46 DC_COM_PIN_OUTPUT_POLARITY2_0, // 308
47 DC_COM_PIN_OUTPUT_POLARITY3_0, // 309
48 DC_COM_PIN_OUTPUT_DATA0_0, // 30A
49 DC_COM_PIN_OUTPUT_DATA1_0, // 30B
50 DC_COM_PIN_OUTPUT_DATA2_0, // 30C
51 DC_COM_PIN_OUTPUT_DATA3_0, // 30D
52 DC_COM_PIN_INPUT_ENABLE0_0, // 30E
53 DC_COM_PIN_INPUT_ENABLE1_0, // 30F
54 DC_COM_PIN_INPUT_ENABLE2_0, // 310
55 DC_COM_PIN_INPUT_ENABLE3_0, // 311
56 DC_COM_PIN_INPUT_DATA0_0, // 312
57 DC_COM_PIN_INPUT_DATA1_0, // 313
58 DC_COM_PIN_OUTPUT_SELECT0_0, // 314
59 DC_COM_PIN_OUTPUT_SELECT1_0, // 315
60 DC_COM_PIN_OUTPUT_SELECT2_0, // 316
61 DC_COM_PIN_OUTPUT_SELECT3_0, // 317
62 DC_COM_PIN_OUTPUT_SELECT4_0, // 318
63 DC_COM_PIN_OUTPUT_SELECT5_0, // 319
64 DC_COM_PIN_OUTPUT_SELECT6_0, // 31A
65 DC_COM_PIN_MISC_CONTROL_0, // 31B
68 DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
69 DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401
70 DC_DISP_DISP_WIN_OPTIONS_0, // 402
71 DC_DISP_MEM_HIGH_PRIORITY_0, // 403
72 DC_DISP_MEM_HIGH_PRIORITY_TIMER_0, // 404
73 DC_DISP_DISP_TIMING_OPTIONS_0, // 405
74 DC_DISP_REF_TO_SYNC_0, // 406 (TrimSlice 0x0001 000B)
75 DC_DISP_SYNC_WIDTH_0, // 407 (TrimSlice 0x0004 003A)
76 DC_DISP_BACK_PORCH_0, // 408 (TrimSlice 0x0004 003A)
77 DC_DISP_DISP_ACTIVE_0, // 409 (TrimSlice 0x0300 0400)
78 DC_DISP_FRONT_PORCH_0, // 40A (TrimSlice 0x0004 003A)
79 DC_DISP_H_PULSE0_CONTROL_0, // 40B
80 DC_DISP_H_PULSE0_POSITION_A_0, // 40C
81 DC_DISP_H_PULSE0_POSITION_B_0, // 40D
82 DC_DISP_H_PULSE0_POSITION_C_0, // 40E
83 DC_DISP_H_PULSE0_POSITION_D_0, // 40F
84 DC_DISP_H_PULSE1_CONTROL_0, // 410
85 DC_DISP_H_PULSE1_POSITION_A_0, // 411
86 DC_DISP_H_PULSE1_POSITION_B_0, // 412
87 DC_DISP_H_PULSE1_POSITION_C_0, // 413
88 DC_DISP_H_PULSE1_POSITION_D_0, // 414
89 DC_DISP_H_PULSE2_CONTROL_0, // 415
90 DC_DISP_H_PULSE2_POSITION_A_0, // 416
91 DC_DISP_H_PULSE2_POSITION_B_0, // 417
92 DC_DISP_H_PULSE2_POSITION_C_0, // 418
93 DC_DISP_H_PULSE2_POSITION_D_0, // 419
94 DC_DISP_V_PULSE0_CONTROL_0, // 41A
95 DC_DISP_V_PULSE0_POSITION_A_0, // 41B
96 DC_DISP_V_PULSE0_POSITION_B_0, // 41C
97 DC_DISP_V_PULSE0_POSITION_C_0, // 41D
98 DC_DISP_V_PULSE1_CONTROL_0, // 41E
99 DC_DISP_V_PULSE1_POSITION_A_0, // 41F
100 DC_DISP_V_PULSE1_POSITION_B_0, // 420
101 DC_DISP_V_PULSE1_POSITION_C_0, // 421
102 DC_DISP_V_PULSE2_CONTROL_0, // 422
103 DC_DISP_V_PULSE2_POSITION_A_0, // 423
104 DC_DISP_V_PULSE3_CONTROL_0, // 424
105 DC_DISP_V_PULSE3_POSITION_A_0, // 425
106 DC_DISP_M0_CONTROL_0, // 426
107 DC_DISP_M1_CONTROL_0, // 427
108 DC_DISP_DI_CONTROL_0, // 428
109 DC_DISP_PP_CONTROL_0, // 429
110 DC_DISP_PP_SELECT_A_0, // 42A
111 DC_DISP_PP_SELECT_B_0, // 42B
112 DC_DISP_PP_SELECT_C_0, // 42C
113 DC_DISP_PP_SELECT_D_0, // 42D
114 DC_DISP_DISP_CLOCK_CONTROL_0, // 42E
115 DC_DISP_DISP_INTERFACE_CONTROL_0,//42F
116 DC_DISP_DISP_COLOR_CONTROL_0, // 430
117 DC_DISP_SHIFT_CLOCK_OPTIONS_0, // 431
118 DC_DISP_DATA_ENABLE_OPTIONS_0, // 432
119 DC_DISP_SERIAL_INTERFACE_OPTIONS_0, // 433
120 DC_DISP_LCD_SPI_OPTIONS_0, // 434
121 DC_DISP_BORDER_COLOR_0, // 435
122 DC_DISP_COLOR_KEY0_LOWER_0, // 436
123 DC_DISP_COLOR_KEY0_UPPER_0, // 437
124 DC_DISP_COLOR_KEY1_LOWER_0, // 438
125 DC_DISP_COLOR_KEY1_UPPER_0, // 439
128 DC_DISP_CURSOR_FOREGROUND_0, // 43C - IMPORTANT
129 DC_DISP_CURSOR_BACKGROUND_0, // 43D - IMPORTANT
130 DC_DISP_CURSOR_START_ADDR_0, // 43E - IMPORTANT
131 DC_DISP_CURSOR_START_ADDR_NS_0, // 43F - IMPORTANT
132 DC_DISP_CURSOR_POSITION_0, // 440 - IMPORTANT
133 DC_DISP_CURSOR_POSITION_NS_0, // 441 - IMPORTANT
134 DC_DISP_INIT_SEQ_CONTROL_0, // 442
135 DC_DISP_SPI_INIT_SEQ_DATA_A_0, // 443
136 DC_DISP_SPI_INIT_SEQ_DATA_B_0, // 444
137 DC_DISP_SPI_INIT_SEQ_DATA_C_0, // 445
138 DC_DISP_SPI_INIT_SEQ_DATA_D_0, // 446
140 DC_DISP_DC_MCCIF_FIFOCTRL_0 = 0x480,
141 DC_DISP_MCCIF_DISPLAY0A_HYST_0, // 481
142 DC_DISP_MCCIF_DISPLAY0B_HYST_0, // 482
143 DC_DISP_MCCIF_DISPLAY0C_HYST_0, // 483
144 DC_DISP_MCCIF_DISPLAY1B_HYST_0, // 484
146 DC_DISP_DAC_CRT_CTRL_0 = 0x4C0,
147 DC_DISP_DISP_MISC_CONTROL_0, // 4C1
149 DC_WINC_A_COLOR_PALETTE_0 = 0x500,
150 DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
151 DC_WIN_A_WIN_OPTIONS_0 = 0x700,
152 DC_WIN_A_BYTE_SWAP_0, // 701
153 DC_WIN_A_BUFFER_CONTROL_0, // 702
154 DC_WIN_A_COLOR_DEPTH_0, // 703
155 DC_WIN_A_POSITION_0, // 704
156 DC_WIN_A_SIZE_0, // 705 (TrimSlice 0x0300 0400)
157 DC_WIN_A_PRESCALED_SIZE_0,
158 DC_WIN_A_H_INITIAL_DDA_0,
159 DC_WIN_A_V_INITIAL_DDA_0,
160 DC_WIN_A_DDA_INCREMENT_0,
161 DC_WIN_A_LINE_STRIDE_0,
162 DC_WIN_A_BUF_STRIDE_0,
163 DC_WIN_A_BUFFER_ADDR_MODE_0,
164 DC_WIN_A_DV_CONTROL_0,
165 DC_WIN_A_BLEND_NOKEY_0,
166 DC_WIN_A_BLEND_1WIN_0,
167 DC_WIN_A_BLEND_2WIN_B_0,
168 DC_WIN_A_BLEND_2WIN_C_0,
169 DC_WIN_A_BLEND_3WIN_BC_0,
170 DC_WIN_A_HP_FETCH_CONTROL_0,
173 DC_WINBUF_A_START_ADDR_0 = 0x800,
174 DC_WINBUF_A_START_ADDR_NS_0,
175 DC_WINBUF_A_ADDR_H_OFFSET_0,
176 DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
177 DC_WINBUF_A_ADDR_V_OFFSET_0,
178 DC_WINBUF_A_ADDR_V_OFFSET_NS_0,
181 #if DEBUG || DUMP_REGISTERS
182 const char * const csaTegra2Vid_RegisterNames[] = {
183 [0x000] = "DC_CMD_GENERAL_INCR_SYNCPT_0",
184 "DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0",
185 "DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0",
186 [0x008] = "DC_CMD_WIN_A_INCR_SYNCPT_0",
187 "DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0",
188 "DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0",
189 [0x010] = "DC_CMD_WIN_B_INCR_SYNCPT_0",
190 "DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0",
191 "DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0",
192 [0x018] = "DC_CMD_WIN_C_INCR_SYNCPT_0",
193 "DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0",
194 "DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0",
195 [0x028] = "DC_CMD_CONT_SYNCPT_VSYNC_0",
196 [0x030] = "DC_CMD_CTXSW_0",
197 "DC_CMD_DISPLAY_COMMAND_OPTION0_0",
198 "DC_CMD_DISPLAY_COMMAND_0",
199 "DC_CMD_SIGNAL_RAISE_0",
200 [0x036] = "DC_CMD_DISPLAY_POWER_CONTROL_0",
201 "DC_CMD_INT_STATUS_0",
203 "DC_CMD_INT_ENABLE_0",
205 "DC_CMD_INT_POLARITY_0",
206 "DC_CMD_SIGNAL_RAISE1_0",
207 "DC_CMD_SIGNAL_RAISE2_0",
208 "DC_CMD_SIGNAL_RAISE3_0",
210 [0x040] = "DC_CMD_STATE_ACCESS_0",
211 "DC_CMD_STATE_CONTROL_0",
212 "DC_CMD_DISPLAY_WINDOW_HEADER_0", // 042
213 "DC_CMD_REG_ACT_CONTROL_0", // 043
215 [0x300] = "DC_COM_CRC_CONTROL_0",
216 "DC_COM_CRC_CHECKSUM_0", // 301
217 "DC_COM_PIN_OUTPUT_ENABLE0_0", // 302
218 "DC_COM_PIN_OUTPUT_ENABLE1_0", // 303
219 "DC_COM_PIN_OUTPUT_ENABLE2_0", // 304
220 "DC_COM_PIN_OUTPUT_ENABLE3_0", // 305
221 "DC_COM_PIN_OUTPUT_POLARITY0_0", // 306
222 "DC_COM_PIN_OUTPUT_POLARITY1_0", // 307
223 "DC_COM_PIN_OUTPUT_POLARITY2_0", // 308
224 "DC_COM_PIN_OUTPUT_POLARITY3_0", // 309
225 "DC_COM_PIN_OUTPUT_DATA0_0", // 30A
226 "DC_COM_PIN_OUTPUT_DATA1_0", // 30B
227 "DC_COM_PIN_OUTPUT_DATA2_0", // 30C
228 "DC_COM_PIN_OUTPUT_DATA3_0", // 30D
229 "DC_COM_PIN_INPUT_ENABLE0_0", // 30E
230 "DC_COM_PIN_INPUT_ENABLE1_0", // 30F
231 "DC_COM_PIN_INPUT_ENABLE2_0", // 310
232 "DC_COM_PIN_INPUT_ENABLE3_0", // 311
233 "DC_COM_PIN_INPUT_DATA0_0", // 312
234 "DC_COM_PIN_INPUT_DATA1_0", // 313
235 "DC_COM_PIN_OUTPUT_SELECT0_0", // 314
236 "DC_COM_PIN_OUTPUT_SELECT1_0", // 315
237 "DC_COM_PIN_OUTPUT_SELECT2_0", // 316
238 "DC_COM_PIN_OUTPUT_SELECT3_0", // 317
239 "DC_COM_PIN_OUTPUT_SELECT4_0", // 318
240 "DC_COM_PIN_OUTPUT_SELECT5_0", // 319
241 "DC_COM_PIN_OUTPUT_SELECT6_0", // 31A
242 "DC_COM_PIN_MISC_CONTROL_0", // 31B
245 [0x400] = "DC_DISP_DISP_SIGNAL_OPTIONS0_0",
246 "DC_DISP_DISP_SIGNAL_OPTIONS1_0", // 401
247 "DC_DISP_DISP_WIN_OPTIONS_0", // 402
248 "DC_DISP_MEM_HIGH_PRIORITY_0", // 403
249 "DC_DISP_MEM_HIGH_PRIORITY_TIMER_0", // 404
250 "DC_DISP_DISP_TIMING_OPTIONS_0", // 405
251 "DC_DISP_REF_TO_SYNC_0", // 406 (TrimSlice 0x0001 000B)
252 "DC_DISP_SYNC_WIDTH_0", // 407 (TrimSlice 0x0004 003A)
253 "DC_DISP_BACK_PORCH_0", // 408 (TrimSlice 0x0004 003A)
254 "DC_DISP_DISP_ACTIVE_0", // 409 (TrimSlice 0x0300 0400)
255 "DC_DISP_FRONT_PORCH_0", // 40A (TrimSlice 0x0004 003A)
256 "DC_DISP_H_PULSE0_CONTROL_0", // 40B
257 "DC_DISP_H_PULSE0_POSITION_A_0", // 40C
258 "DC_DISP_H_PULSE0_POSITION_B_0", // 40D
259 "DC_DISP_H_PULSE0_POSITION_C_0", // 40E
260 "DC_DISP_H_PULSE0_POSITION_D_0", // 40F
261 "DC_DISP_H_PULSE1_CONTROL_0", // 410
262 "DC_DISP_H_PULSE1_POSITION_A_0", // 411
263 "DC_DISP_H_PULSE1_POSITION_B_0", // 412
264 "DC_DISP_H_PULSE1_POSITION_C_0", // 413
265 "DC_DISP_H_PULSE1_POSITION_D_0", // 414
266 "DC_DISP_H_PULSE2_CONTROL_0", // 415
267 "DC_DISP_H_PULSE2_POSITION_A_0", // 416
268 "DC_DISP_H_PULSE2_POSITION_B_0", // 417
269 "DC_DISP_H_PULSE2_POSITION_C_0", // 418
270 "DC_DISP_H_PULSE2_POSITION_D_0", // 419
271 "DC_DISP_V_PULSE0_CONTROL_0", // 41A
272 "DC_DISP_V_PULSE0_POSITION_A_0", // 41B
273 "DC_DISP_V_PULSE0_POSITION_B_0", // 41C
274 "DC_DISP_V_PULSE0_POSITION_C_0", // 41D
275 "DC_DISP_V_PULSE1_CONTROL_0", // 41E
276 "DC_DISP_V_PULSE1_POSITION_A_0", // 41F
277 "DC_DISP_V_PULSE1_POSITION_B_0", // 420
278 "DC_DISP_V_PULSE1_POSITION_C_0", // 421
279 "DC_DISP_V_PULSE2_CONTROL_0", // 422
280 "DC_DISP_V_PULSE2_POSITION_A_0", // 423
281 "DC_DISP_V_PULSE3_CONTROL_0", // 424
282 "DC_DISP_V_PULSE3_POSITION_A_0", // 425
283 "DC_DISP_M0_CONTROL_0", // 426
284 "DC_DISP_M1_CONTROL_0", // 427
285 "DC_DISP_DI_CONTROL_0", // 428
286 "DC_DISP_PP_CONTROL_0", // 429
287 "DC_DISP_PP_SELECT_A_0", // 42A
288 "DC_DISP_PP_SELECT_B_0", // 42B
289 "DC_DISP_PP_SELECT_C_0", // 42C
290 "DC_DISP_PP_SELECT_D_0", // 42D
291 "DC_DISP_DISP_CLOCK_CONTROL_0", // 42E
292 "DC_DISP_DISP_INTERFACE_CONTROL_0",//42F
293 "DC_DISP_DISP_COLOR_CONTROL_0", // 430
294 "DC_DISP_SHIFT_CLOCK_OPTIONS_0", // 431
295 "DC_DISP_DATA_ENABLE_OPTIONS_0", // 432
296 "DC_DISP_SERIAL_INTERFACE_OPTIONS_0", // 433
297 "DC_DISP_LCD_SPI_OPTIONS_0", // 434
298 "DC_DISP_BORDER_COLOR_0", // 435
299 "DC_DISP_COLOR_KEY0_LOWER_0", // 436
300 "DC_DISP_COLOR_KEY0_UPPER_0", // 437
301 "DC_DISP_COLOR_KEY1_LOWER_0", // 438
302 "DC_DISP_COLOR_KEY1_UPPER_0", // 439
303 "_DC_DISP_UNUSED_43A",
304 "_DC_DISP_UNUSED_43B",
305 "DC_DISP_CURSOR_FOREGROUND_0", // 43C - IMPORTANT
306 "DC_DISP_CURSOR_BACKGROUND_0", // 43D - IMPORTANT
307 "DC_DISP_CURSOR_START_ADDR_0", // 43E - IMPORTANT
308 "DC_DISP_CURSOR_START_ADDR_NS_0", // 43F - IMPORTANT
309 "DC_DISP_CURSOR_POSITION_0", // 440 - IMPORTANT
310 "DC_DISP_CURSOR_POSITION_NS_0", // 441 - IMPORTANT
311 "DC_DISP_INIT_SEQ_CONTROL_0", // 442
312 "DC_DISP_SPI_INIT_SEQ_DATA_A_0", // 443
313 "DC_DISP_SPI_INIT_SEQ_DATA_B_0", // 444
314 "DC_DISP_SPI_INIT_SEQ_DATA_C_0", // 445
315 "DC_DISP_SPI_INIT_SEQ_DATA_D_0", // 446
317 [0x480] = "DC_DISP_DC_MCCIF_FIFOCTRL_0",
318 "DC_DISP_MCCIF_DISPLAY0A_HYST_0", // 481
319 "DC_DISP_MCCIF_DISPLAY0B_HYST_0", // 482
320 "DC_DISP_MCCIF_DISPLAY0C_HYST_0", // 483
321 "DC_DISP_MCCIF_DISPLAY1B_HYST_0", // 484
323 [0x4C0] = "DC_DISP_DAC_CRT_CTRL_0",
324 "DC_DISP_DISP_MISC_CONTROL_0", // 4C1
326 [0x500] = "DC_WINC_A_COLOR_PALETTE_0",
327 [0x600] = "DC_WINC_A_PALETTE_COLOR_EXT_0",
328 [0x700] = "DC_WIN_A_WIN_OPTIONS_0",
329 "DC_WIN_A_BYTE_SWAP_0", // 701
330 "DC_WIN_A_BUFFER_CONTROL_0", // 702
331 "DC_WIN_A_COLOR_DEPTH_0", // 703
332 "DC_WIN_A_POSITION_0", // 704
333 "DC_WIN_A_SIZE_0", // 705 (TrimSlice 0x0300 0400)
334 "DC_WIN_A_PRESCALED_SIZE_0",
335 "DC_WIN_A_H_INITIAL_DDA_0",
336 "DC_WIN_A_V_INITIAL_DDA_0",
337 "DC_WIN_A_DDA_INCREMENT_0",
338 "DC_WIN_A_LINE_STRIDE_0",
339 "DC_WIN_A_BUF_STRIDE_0",
340 "DC_WIN_A_BUFFER_ADDR_MODE_0",
341 "DC_WIN_A_DV_CONTROL_0",
342 "DC_WIN_A_BLEND_NOKEY_0",
343 "DC_WIN_A_BLEND_1WIN_0",
344 "DC_WIN_A_BLEND_2WIN_B_0",
345 "DC_WIN_A_BLEND_2WIN_C_0",
346 "DC_WIN_A_BLEND_3WIN_BC_0",
347 "DC_WIN_A_HP_FETCH_CONTROL_0",
349 [0x800] = "DC_WINBUF_A_START_ADDR_0",
350 [0x801] = "DC_WINBUF_A_START_ADDR_NS_0",
351 [0x806] = "DC_WINBUF_A_ADDR_H_OFFSET_0",
352 [0x807] = "DC_WINBUF_A_ADDR_H_OFFSET_NS_0",
353 [0x808] = "DC_WINBUF_A_ADDR_V_OFFSET_0",
354 [0x809] = "DC_WINBUF_A_ADDR_V_OFFSET_NS_0",
355 [0x80A] = "DC_WINBUF_A_UFLOW_STATUS"
360 /// \name DC_CMD_STATE_CONTROL_0
362 #define GEN_ACT_REQ 0x0001
363 #define WIN_A_ACT_REQ 0x0002
364 #define WIN_B_ACT_REQ 0x0004
365 #define WIN_C_ACT_REQ 0x0008