KernelLand/Modules/Display/Tegra2Vid/tegra2.h

   1 /*
   2  * Acess2 NVidia Tegra2 Display Driver
   3  * - By John Hodge (thePowersGang)
   4  *
   5  * tegra2.h
   6  * - Driver definitions
   7  */
   8 #ifndef _TEGRA2_DISP_H_
   9 #define _TEGRA2_DISP_H_
  10
  11 #define TEGRA2VID_BASE  0x54200000      // 0x40000 Large (256 KB)
  12
  13 const struct sTegra2_Disp_Mode
  14 {
  15         Uint16  W,   H;
  16         Uint16  HFP, VFP;
  17         Uint16  HS,  VS;
  18         Uint16  HBP, VBP;
  19 }       caTegra2Vid_Modes[] = {
  20         // TODO: VESA timings
  21         {1024, 768,  58, 4,   58,  4,   58,   4},       // 1024x768 (reset), RtS=11,4
  22         {1680,1050, 104, 1,  184,  3 , 288,  33},       // 1680x1050 @ 60Hz
  23         // TV Timings
  24         {720,  487,  16,33,   63, 33,   59, 133},       // NTSC 2
  25         {720,  576,  12,33,   63, 33,   69, 193},       // PAL 2 (VFP shown as 2/33, used 33)
  26         {720,  483,  16, 6,   63,  6,   59,  30},       // 480p
  27         {1280, 720,  70, 5,  804,  6,  220,  20},       // 720p
  28         {1920,1080,  44, 4,  884,  5,  148,  36},       // 1080p
  29         // TODO: Can all but HA/VA be constant and those select the resolution?
  30 };
  31 const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
  32
  33 enum eTegra2_Disp_Regs
  34 {
  35         DC_CMD_STATE_CONTROL_0 = 0x041,
  36         DC_CMD_DISPLAY_WINDOW_HEADER_0, // 042
  37         DC_CMD_REG_ACT_CONTROL_0,       // 043
  38
  39         DC_COM_CRC_CONTROL_0 = 0x300,
  40         DC_COM_CRC_CHECKSUM_0,          // 301
  41         DC_COM_PIN_OUTPUT_ENABLE0_0,    // 302
  42         DC_COM_PIN_OUTPUT_ENABLE1_0,    // 303
  43         DC_COM_PIN_OUTPUT_ENABLE2_0,    // 304
  44         DC_COM_PIN_OUTPUT_ENABLE3_0,    // 305
  45         DC_COM_PIN_OUTPUT_POLARITY0_0,  // 306
  46         DC_COM_PIN_OUTPUT_POLARITY1_0,  // 307
  47         DC_COM_PIN_OUTPUT_POLARITY2_0,  // 308
  48         DC_COM_PIN_OUTPUT_POLARITY3_0,  // 309
  49         DC_COM_PIN_OUTPUT_DATA0_0,      // 30A
  50         DC_COM_PIN_OUTPUT_DATA1_0,      // 30B
  51         DC_COM_PIN_OUTPUT_DATA2_0,      // 30C
  52         DC_COM_PIN_OUTPUT_DATA3_0,      // 30D
  53         DC_COM_PIN_INPUT_ENABLE0_0,     // 30E
  54         DC_COM_PIN_INPUT_ENABLE1_0,     // 30F
  55         DC_COM_PIN_INPUT_ENABLE2_0,     // 310
  56         DC_COM_PIN_INPUT_ENABLE3_0,     // 311
  57         DC_COM_PIN_INPUT_DATA0_0,       // 312
  58         DC_COM_PIN_INPUT_DATA1_0,       // 313
  59         DC_COM_PIN_OUTPUT_SELECT0_0,    // 314
  60         DC_COM_PIN_OUTPUT_SELECT1_0,    // 315
  61         DC_COM_PIN_OUTPUT_SELECT2_0,    // 316
  62         DC_COM_PIN_OUTPUT_SELECT3_0,    // 317
  63         DC_COM_PIN_OUTPUT_SELECT4_0,    // 318
  64         DC_COM_PIN_OUTPUT_SELECT5_0,    // 319
  65         DC_COM_PIN_OUTPUT_SELECT6_0,    // 31A
  66         DC_COM_PIN_MISC_CONTROL_0,      // 31B
  67         // TODO: Complete
  68
  69         DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
  70         DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401
  71         DC_DISP_DISP_WIN_OPTIONS_0,     // 402
  72         DC_DISP_MEM_HIGH_PRIORITY_0,    // 403
  73         DC_DISP_MEM_HIGH_PRIORITY_TIMER_0,      // 404
  74         DC_DISP_DISP_TIMING_OPTIONS_0,  // 405
  75         DC_DISP_REF_TO_SYNC_0,          // 406 (TrimSlice 0x0001 000B)
  76         DC_DISP_SYNC_WIDTH_0,           // 407 (TrimSlice 0x0004 003A)
  77         DC_DISP_BACK_PORCH_0,           // 408 (TrimSlice 0x0004 003A)
  78         DC_DISP_DISP_ACTIVE_0,          // 409 (TrimSlice 0x0300 0400)
  79         DC_DISP_FRONT_PORCH_0,          // 40A (TrimSlice 0x0004 003A)
  80         DC_DISP_H_PULSE0_CONTROL_0,     // 40B
  81         DC_DISP_H_PULSE0_POSITION_A_0,  // 40C
  82         DC_DISP_H_PULSE0_POSITION_B_0,  // 40D
  83         DC_DISP_H_PULSE0_POSITION_C_0,  // 40E
  84         DC_DISP_H_PULSE0_POSITION_D_0,  // 40F
  85         DC_DISP_H_PULSE1_CONTROL_0,     // 410
  86         DC_DISP_H_PULSE1_POSITION_A_0,  // 411
  87         DC_DISP_H_PULSE1_POSITION_B_0,  // 412
  88         DC_DISP_H_PULSE1_POSITION_C_0,  // 413
  89         DC_DISP_H_PULSE1_POSITION_D_0,  // 414
  90         DC_DISP_H_PULSE2_CONTROL_0,     // 415
  91         DC_DISP_H_PULSE2_POSITION_A_0,  // 416
  92         DC_DISP_H_PULSE2_POSITION_B_0,  // 417
  93         DC_DISP_H_PULSE2_POSITION_C_0,  // 418
  94         DC_DISP_H_PULSE2_POSITION_D_0,  // 419
  95         DC_DISP_V_PULSE0_CONTROL_0,     // 41A
  96         DC_DISP_V_PULSE0_POSITION_A_0,  // 41B
  97         DC_DISP_V_PULSE0_POSITION_B_0,  // 41C
  98         DC_DISP_V_PULSE0_POSITION_C_0,  // 41D
  99         DC_DISP_V_PULSE1_CONTROL_0,     // 41E
 100         DC_DISP_V_PULSE1_POSITION_A_0,  // 41F
 101         DC_DISP_V_PULSE1_POSITION_B_0,  // 420
 102         DC_DISP_V_PULSE1_POSITION_C_0,  // 421
 103         DC_DISP_V_PULSE2_CONTROL_0,     // 422
 104         DC_DISP_V_PULSE2_POSITION_A_0,  // 423
 105         DC_DISP_V_PULSE3_CONTROL_0,     // 424
 106         DC_DISP_V_PULSE3_POSITION_A_0,  // 425
 107         DC_DISP_M0_CONTROL_0,           // 426
 108         DC_DISP_M1_CONTROL_0,           // 427
 109         DC_DISP_DI_CONTROL_0,           // 428
 110         DC_DISP_PP_CONTROL_0,           // 429
 111         DC_DISP_PP_SELECT_A_0,          // 42A
 112         DC_DISP_PP_SELECT_B_0,          // 42B
 113         DC_DISP_PP_SELECT_C_0,          // 42C
 114         DC_DISP_PP_SELECT_D_0,          // 42D
 115         DC_DISP_DISP_CLOCK_CONTROL_0,   // 42E
 116         DC_DISP_DISP_INTERFACE_CONTROL_0,//42F
 117         DC_DISP_DISP_COLOR_CONTROL_0,   // 430
 118         DC_DISP_SHIFT_CLOCK_OPTIONS_0,  // 431
 119         DC_DISP_DATA_ENABLE_OPTIONS_0,  // 432
 120         DC_DISP_SERIAL_INTERFACE_OPTIONS_0,     // 433
 121         DC_DISP_LCD_SPI_OPTIONS_0,      // 434
 122         DC_DISP_BORDER_COLOR_0,         // 435
 123         DC_DISP_COLOR_KEY0_LOWER_0,     // 436
 124         DC_DISP_COLOR_KEY0_UPPER_0,     // 437
 125         DC_DISP_COLOR_KEY1_LOWER_0,     // 438
 126         DC_DISP_COLOR_KEY1_UPPER_0,     // 439
 127         _DC_DISP_UNUSED_43A,
 128         _DC_DISP_UNUSED_43B,
 129         DC_DISP_CURSOR_FOREGROUND_0,    // 43C - IMPORTANT
 130         DC_DISP_CURSOR_BACKGROUND_0,    // 43D - IMPORTANT
 131         DC_DISP_CURSOR_START_ADDR_0,    // 43E - IMPORTANT
 132         DC_DISP_CURSOR_START_ADDR_NS_0, // 43F - IMPORTANT
 133         DC_DISP_CURSOR_POSITION_0,      // 440 - IMPORTANT
 134         DC_DISP_CURSOR_POSITION_NS_0,   // 441 - IMPORTANT
 135         DC_DISP_INIT_SEQ_CONTROL_0,     // 442
 136         DC_DISP_SPI_INIT_SEQ_DATA_A_0,  // 443
 137         DC_DISP_SPI_INIT_SEQ_DATA_B_0,  // 444
 138         DC_DISP_SPI_INIT_SEQ_DATA_C_0,  // 445
 139         DC_DISP_SPI_INIT_SEQ_DATA_D_0,  // 446
 140
 141         DC_DISP_DC_MCCIF_FIFOCTRL_0 = 0x480,
 142         DC_DISP_MCCIF_DISPLAY0A_HYST_0, // 481
 143         DC_DISP_MCCIF_DISPLAY0B_HYST_0, // 482
 144         DC_DISP_MCCIF_DISPLAY0C_HYST_0, // 483
 145         DC_DISP_MCCIF_DISPLAY1B_HYST_0, // 484
 146
 147         DC_DISP_DAC_CRT_CTRL_0 = 0x4C0,
 148         DC_DISP_DISP_MISC_CONTROL_0,    // 4C1
 149
 150         DC_WINC_A_COLOR_PALETTE_0 = 0x500,
 151         DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
 152         DC_WIN_A_WIN_OPTIONS_0 = 0x700,
 153         DC_WIN_A_BYTE_SWAP_0,           // 701
 154         DC_WIN_A_BUFFER_CONTROL_0,      // 702
 155         DC_WIN_A_COLOR_DEPTH_0,         // 703
 156         DC_WIN_A_POSITION_0,            // 704
 157         DC_WIN_A_SIZE_0,                // 705 (TrimSlice 0x0300 0400)
 158         DC_WIN_A_PRESCALED_SIZE_0,
 159         DC_WIN_A_H_INITIAL_DDA_0,
 160         DC_WIN_A_V_INITIAL_DDA_0,
 161         DC_WIN_A_DDA_INCREMENT_0,
 162         DC_WIN_A_LINE_STRIDE_0,
 163         DC_WIN_A_BUF_STRIDE_0,
 164         _DC_WIN_A_70C,
 165         DC_WIN_A_BUFFER_ADDR_MODE_0,
 166         DC_WIN_A_DV_CONTROL_0,
 167         DC_WIN_A_BLEND_NOKEY_0,
 168         DC_WIN_A_BLEND_1WIN_0,
 169         DC_WIN_A_BLEND_2WIN_B_0,
 170         DC_WIN_A_BLEND_2WIN_C_0,
 171         DC_WIN_A_BLEND_3WIN_BC_0,
 172         DC_WIN_A_HP_FETCH_CONTROL_0,
 173
 174
 175         DC_WINBUF_A_START_ADDR_0 = 0x800,
 176         DC_WINBUF_A_START_ADDR_NS_0,
 177         DC_WINBUF_A_ADDR_H_OFFSET_0,
 178         DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
 179         DC_WINBUF_A_ADDR_V_OFFSET_0,
 180         DC_WINBUF_A_ADDR_V_OFFSET_NS_0,
 181 };
 182
 183 #if DEBUG || DUMP_REGISTERS
 184 const char * const csaTegra2Vid_RegisterNames[] = {
 185         [0x000] = "DC_CMD_GENERAL_INCR_SYNCPT_0",
 186         "DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0",
 187         "DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0",
 188         [0x008] = "DC_CMD_WIN_A_INCR_SYNCPT_0",
 189         "DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0",
 190         "DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0",
 191         [0x010] = "DC_CMD_WIN_B_INCR_SYNCPT_0",
 192         "DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0",
 193         "DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0",
 194         [0x018] = "DC_CMD_WIN_C_INCR_SYNCPT_0",
 195         "DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0",
 196         "DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0",
 197         [0x028] = "DC_CMD_CONT_SYNCPT_VSYNC_0",
 198         [0x030] = "DC_CMD_CTXSW_0",
 199         "DC_CMD_DISPLAY_COMMAND_OPTION0_0",
 200         "DC_CMD_DISPLAY_COMMAND_0",
 201         "DC_CMD_SIGNAL_RAISE_0",
 202         [0x036] = "DC_CMD_DISPLAY_POWER_CONTROL_0",
 203         "DC_CMD_INT_STATUS_0",
 204         "DC_CMD_INT_MASK_0",
 205         "DC_CMD_INT_ENABLE_0",
 206         "DC_CMD_INT_TYPE_0",
 207         "DC_CMD_INT_POLARITY_0",
 208         "DC_CMD_SIGNAL_RAISE1_0",
 209         "DC_CMD_SIGNAL_RAISE2_0",
 210         "DC_CMD_SIGNAL_RAISE3_0",
 211
 212         [0x040] = "DC_CMD_STATE_ACCESS_0",
 213         "DC_CMD_STATE_CONTROL_0",
 214         "DC_CMD_DISPLAY_WINDOW_HEADER_0",       // 042
 215         "DC_CMD_REG_ACT_CONTROL_0",     // 043
 216
 217         [0x300] = "DC_COM_CRC_CONTROL_0",
 218         "DC_COM_CRC_CHECKSUM_0",        // 301
 219         "DC_COM_PIN_OUTPUT_ENABLE0_0",  // 302
 220         "DC_COM_PIN_OUTPUT_ENABLE1_0",  // 303
 221         "DC_COM_PIN_OUTPUT_ENABLE2_0",  // 304
 222         "DC_COM_PIN_OUTPUT_ENABLE3_0",  // 305
 223         "DC_COM_PIN_OUTPUT_POLARITY0_0",        // 306
 224         "DC_COM_PIN_OUTPUT_POLARITY1_0",        // 307
 225         "DC_COM_PIN_OUTPUT_POLARITY2_0",        // 308
 226         "DC_COM_PIN_OUTPUT_POLARITY3_0",        // 309
 227         "DC_COM_PIN_OUTPUT_DATA0_0",    // 30A
 228         "DC_COM_PIN_OUTPUT_DATA1_0",    // 30B
 229         "DC_COM_PIN_OUTPUT_DATA2_0",    // 30C
 230         "DC_COM_PIN_OUTPUT_DATA3_0",    // 30D
 231         "DC_COM_PIN_INPUT_ENABLE0_0",   // 30E
 232         "DC_COM_PIN_INPUT_ENABLE1_0",   // 30F
 233         "DC_COM_PIN_INPUT_ENABLE2_0",   // 310
 234         "DC_COM_PIN_INPUT_ENABLE3_0",   // 311
 235         "DC_COM_PIN_INPUT_DATA0_0",     // 312
 236         "DC_COM_PIN_INPUT_DATA1_0",     // 313
 237         "DC_COM_PIN_OUTPUT_SELECT0_0",  // 314
 238         "DC_COM_PIN_OUTPUT_SELECT1_0",  // 315
 239         "DC_COM_PIN_OUTPUT_SELECT2_0",  // 316
 240         "DC_COM_PIN_OUTPUT_SELECT3_0",  // 317
 241         "DC_COM_PIN_OUTPUT_SELECT4_0",  // 318
 242         "DC_COM_PIN_OUTPUT_SELECT5_0",  // 319
 243         "DC_COM_PIN_OUTPUT_SELECT6_0",  // 31A
 244         "DC_COM_PIN_MISC_CONTROL_0",    // 31B
 245         // TODO: Complete
 246
 247         [0x400] = "DC_DISP_DISP_SIGNAL_OPTIONS0_0",
 248         "DC_DISP_DISP_SIGNAL_OPTIONS1_0", // 401
 249         "DC_DISP_DISP_WIN_OPTIONS_0",   // 402
 250         "DC_DISP_MEM_HIGH_PRIORITY_0",  // 403
 251         "DC_DISP_MEM_HIGH_PRIORITY_TIMER_0",    // 404
 252         "DC_DISP_DISP_TIMING_OPTIONS_0",        // 405
 253         "DC_DISP_REF_TO_SYNC_0",        // 406 (TrimSlice 0x0001 000B)
 254         "DC_DISP_SYNC_WIDTH_0",         // 407 (TrimSlice 0x0004 003A)
 255         "DC_DISP_BACK_PORCH_0",         // 408 (TrimSlice 0x0004 003A)
 256         "DC_DISP_DISP_ACTIVE_0",        // 409 (TrimSlice 0x0300 0400)
 257         "DC_DISP_FRONT_PORCH_0",        // 40A (TrimSlice 0x0004 003A)
 258         "DC_DISP_H_PULSE0_CONTROL_0",   // 40B
 259         "DC_DISP_H_PULSE0_POSITION_A_0",        // 40C
 260         "DC_DISP_H_PULSE0_POSITION_B_0",        // 40D
 261         "DC_DISP_H_PULSE0_POSITION_C_0",        // 40E
 262         "DC_DISP_H_PULSE0_POSITION_D_0",        // 40F
 263         "DC_DISP_H_PULSE1_CONTROL_0",   // 410
 264         "DC_DISP_H_PULSE1_POSITION_A_0",        // 411
 265         "DC_DISP_H_PULSE1_POSITION_B_0",        // 412
 266         "DC_DISP_H_PULSE1_POSITION_C_0",        // 413
 267         "DC_DISP_H_PULSE1_POSITION_D_0",        // 414
 268         "DC_DISP_H_PULSE2_CONTROL_0",   // 415
 269         "DC_DISP_H_PULSE2_POSITION_A_0",        // 416
 270         "DC_DISP_H_PULSE2_POSITION_B_0",        // 417
 271         "DC_DISP_H_PULSE2_POSITION_C_0",        // 418
 272         "DC_DISP_H_PULSE2_POSITION_D_0",        // 419
 273         "DC_DISP_V_PULSE0_CONTROL_0",   // 41A
 274         "DC_DISP_V_PULSE0_POSITION_A_0",        // 41B
 275         "DC_DISP_V_PULSE0_POSITION_B_0",        // 41C
 276         "DC_DISP_V_PULSE0_POSITION_C_0",        // 41D
 277         "DC_DISP_V_PULSE1_CONTROL_0",   // 41E
 278         "DC_DISP_V_PULSE1_POSITION_A_0",        // 41F
 279         "DC_DISP_V_PULSE1_POSITION_B_0",        // 420
 280         "DC_DISP_V_PULSE1_POSITION_C_0",        // 421
 281         "DC_DISP_V_PULSE2_CONTROL_0",   // 422
 282         "DC_DISP_V_PULSE2_POSITION_A_0",        // 423
 283         "DC_DISP_V_PULSE3_CONTROL_0",   // 424
 284         "DC_DISP_V_PULSE3_POSITION_A_0",        // 425
 285         "DC_DISP_M0_CONTROL_0",         // 426
 286         "DC_DISP_M1_CONTROL_0",         // 427
 287         "DC_DISP_DI_CONTROL_0",         // 428
 288         "DC_DISP_PP_CONTROL_0",         // 429
 289         "DC_DISP_PP_SELECT_A_0",        // 42A
 290         "DC_DISP_PP_SELECT_B_0",        // 42B
 291         "DC_DISP_PP_SELECT_C_0",        // 42C
 292         "DC_DISP_PP_SELECT_D_0",        // 42D
 293         "DC_DISP_DISP_CLOCK_CONTROL_0", // 42E
 294         "DC_DISP_DISP_INTERFACE_CONTROL_0",//42F
 295         "DC_DISP_DISP_COLOR_CONTROL_0", // 430
 296         "DC_DISP_SHIFT_CLOCK_OPTIONS_0",        // 431
 297         "DC_DISP_DATA_ENABLE_OPTIONS_0",        // 432
 298         "DC_DISP_SERIAL_INTERFACE_OPTIONS_0",   // 433
 299         "DC_DISP_LCD_SPI_OPTIONS_0",    // 434
 300         "DC_DISP_BORDER_COLOR_0",       // 435
 301         "DC_DISP_COLOR_KEY0_LOWER_0",   // 436
 302         "DC_DISP_COLOR_KEY0_UPPER_0",   // 437
 303         "DC_DISP_COLOR_KEY1_LOWER_0",   // 438
 304         "DC_DISP_COLOR_KEY1_UPPER_0",   // 439
 305         "_DC_DISP_UNUSED_43A",
 306         "_DC_DISP_UNUSED_43B",
 307         "DC_DISP_CURSOR_FOREGROUND_0",  // 43C - IMPORTANT
 308         "DC_DISP_CURSOR_BACKGROUND_0",  // 43D - IMPORTANT
 309         "DC_DISP_CURSOR_START_ADDR_0",  // 43E - IMPORTANT
 310         "DC_DISP_CURSOR_START_ADDR_NS_0",       // 43F - IMPORTANT
 311         "DC_DISP_CURSOR_POSITION_0",    // 440 - IMPORTANT
 312         "DC_DISP_CURSOR_POSITION_NS_0", // 441 - IMPORTANT
 313         "DC_DISP_INIT_SEQ_CONTROL_0",   // 442
 314         "DC_DISP_SPI_INIT_SEQ_DATA_A_0",        // 443
 315         "DC_DISP_SPI_INIT_SEQ_DATA_B_0",        // 444
 316         "DC_DISP_SPI_INIT_SEQ_DATA_C_0",        // 445
 317         "DC_DISP_SPI_INIT_SEQ_DATA_D_0",        // 446
 318
 319         [0x480] = "DC_DISP_DC_MCCIF_FIFOCTRL_0",
 320         "DC_DISP_MCCIF_DISPLAY0A_HYST_0",       // 481
 321         "DC_DISP_MCCIF_DISPLAY0B_HYST_0",       // 482
 322         "DC_DISP_MCCIF_DISPLAY0C_HYST_0",       // 483
 323         "DC_DISP_MCCIF_DISPLAY1B_HYST_0",       // 484
 324
 325         [0x4C0] = "DC_DISP_DAC_CRT_CTRL_0",
 326         "DC_DISP_DISP_MISC_CONTROL_0",  // 4C1
 327
 328         [0x500] = "DC_WINC_A_COLOR_PALETTE_0",
 329         [0x600] = "DC_WINC_A_PALETTE_COLOR_EXT_0",
 330         [0x700] = "DC_WIN_A_WIN_OPTIONS_0",
 331         "DC_WIN_A_BYTE_SWAP_0",         // 701
 332         "DC_WIN_A_BUFFER_CONTROL_0",    // 702
 333         "DC_WIN_A_COLOR_DEPTH_0",       // 703
 334         "DC_WIN_A_POSITION_0",          // 704
 335         "DC_WIN_A_SIZE_0",              // 705 (TrimSlice 0x0300 0400)
 336         "DC_WIN_A_PRESCALED_SIZE_0",
 337         "DC_WIN_A_H_INITIAL_DDA_0",
 338         "DC_WIN_A_V_INITIAL_DDA_0",
 339         "DC_WIN_A_DDA_INCREMENT_0",
 340         "DC_WIN_A_LINE_STRIDE_0",
 341         "DC_WIN_A_BUF_STRIDE_0",
 342         "-",
 343         "DC_WIN_A_BUFFER_ADDR_MODE_0",
 344         "DC_WIN_A_DV_CONTROL_0",
 345         "DC_WIN_A_BLEND_NOKEY_0",
 346         "DC_WIN_A_BLEND_1WIN_0",
 347         "DC_WIN_A_BLEND_2WIN_B_0",
 348         "DC_WIN_A_BLEND_2WIN_C_0",
 349         "DC_WIN_A_BLEND_3WIN_BC_0",
 350         "DC_WIN_A_HP_FETCH_CONTROL_0",
 351
 352         [0x800] = "DC_WINBUF_A_START_ADDR_0",
 353         [0x801] = "DC_WINBUF_A_START_ADDR_NS_0",
 354         [0x806] = "DC_WINBUF_A_ADDR_H_OFFSET_0",
 355         [0x807] = "DC_WINBUF_A_ADDR_H_OFFSET_NS_0",
 356         [0x808] = "DC_WINBUF_A_ADDR_V_OFFSET_0",
 357         [0x809] = "DC_WINBUF_A_ADDR_V_OFFSET_NS_0",
 358         [0x80A] = "DC_WINBUF_A_UFLOW_STATUS"
 359 };
 360 #endif
 361
 362 // Bit definitions
 363 /// \name DC_CMD_STATE_CONTROL_0
 364 /// \{
 365 #define GEN_ACT_REQ     0x0001
 366 #define WIN_A_ACT_REQ   0x0002
 367 #define WIN_B_ACT_REQ   0x0004
 368 #define WIN_C_ACT_REQ   0x0008
 369 /// \}
 370
 371 #endif
 372