2 * Acess2 NVidia Tegra2 Display Driver
3 * - By John Hodge (thePowersGang)
8 #ifndef _TEGRA2_DISP_H_
9 #define _TEGRA2_DISP_H_
11 #define TEGRA2VID_BASE 0x54200000 // 0x40000 Large (256 KB)
13 const struct sTegra2_Disp_Mode
19 } caTegra2Vid_Modes[] = {
21 // {720, 487, 16,33, 63, 33, 59, 133}, // NTSC 2
22 // {720, 576, 12,33, 63, 33, 69, 193}, // PAL 2 (VFP shown as 2/33, used 33)
23 // {720, 483, 16, 6, 63, 6, 59, 30}, // 480p
24 // {1280, 720, 70, 5, 804, 6, 220, 20}, // 720p
25 // {1920,1080, 44, 4, 884, 5, 148, 36}, // 1080p
26 // TODO: Can all but HA/VA be constant and those select the resolution?
28 const int ciTegra2Vid_ModeCount = sizeof(caTegra2Vid_Modes)/sizeof(caTegra2Vid_Modes[0]);
30 enum eTegra2_Disp_Regs
32 DC_CMD_STATE_CONTROL_0 = 0x041,
33 DC_CMD_DISPLAY_WINDOW_HEADER_0, // 042
34 DC_CMD_REG_ACT_CONTROL_0, // 043
36 DC_COM_CRC_CONTROL_0 = 0x300,
37 DC_COM_CRC_CHECKSUM_0, // 301
38 DC_COM_PIN_OUTPUT_ENABLE0_0, // 302
39 DC_COM_PIN_OUTPUT_ENABLE1_0, // 303
40 DC_COM_PIN_OUTPUT_ENABLE2_0, // 304
41 DC_COM_PIN_OUTPUT_ENABLE3_0, // 305
42 DC_COM_PIN_OUTPUT_POLARITY0_0, // 306
43 DC_COM_PIN_OUTPUT_POLARITY1_0, // 307
44 DC_COM_PIN_OUTPUT_POLARITY2_0, // 308
45 DC_COM_PIN_OUTPUT_POLARITY3_0, // 309
46 DC_COM_PIN_OUTPUT_DATA0_0, // 30A
47 DC_COM_PIN_OUTPUT_DATA1_0, // 30B
48 DC_COM_PIN_OUTPUT_DATA2_0, // 30C
49 DC_COM_PIN_OUTPUT_DATA3_0, // 30D
50 DC_COM_PIN_INPUT_ENABLE0_0, // 30E
51 DC_COM_PIN_INPUT_ENABLE1_0, // 30F
52 DC_COM_PIN_INPUT_ENABLE2_0, // 310
53 DC_COM_PIN_INPUT_ENABLE3_0, // 311
54 DC_COM_PIN_INPUT_DATA0_0, // 312
55 DC_COM_PIN_INPUT_DATA1_0, // 313
56 DC_COM_PIN_OUTPUT_SELECT0_0, // 314
57 DC_COM_PIN_OUTPUT_SELECT1_0, // 315
58 DC_COM_PIN_OUTPUT_SELECT2_0, // 316
59 DC_COM_PIN_OUTPUT_SELECT3_0, // 317
60 DC_COM_PIN_OUTPUT_SELECT4_0, // 318
61 DC_COM_PIN_OUTPUT_SELECT5_0, // 319
62 DC_COM_PIN_OUTPUT_SELECT6_0, // 31A
63 DC_COM_PIN_MISC_CONTROL_0, // 31B
66 DC_DISP_DISP_SIGNAL_OPTIONS0_0 = 0x400,
67 DC_DISP_DISP_SIGNAL_OPTIONS1_0, // 401
68 DC_DISP_DISP_WIN_OPTIONS_0, // 402
69 DC_DISP_MEM_HIGH_PRIORITY_0, // 403
70 DC_DISP_MEM_HIGH_PRIORITY_TIMER_0, // 404
71 DC_DISP_DISP_TIMING_OPTIONS_0, // 405
72 DC_DISP_REF_TO_SYNC_0, // 406 (TrimSlice 0x0001 000B)
73 DC_DISP_SYNC_WIDTH_0, // 407 (TrimSlice 0x0004 003A)
74 DC_DISP_BACK_PORCH_0, // 408 (TrimSlice 0x0004 003A)
75 DC_DISP_DISP_ACTIVE_0, // 409 (TrimSlice 0x0300 0400)
76 DC_DISP_FRONT_PORCH_0, // 40A (TrimSlice 0x0004 003A)
77 DC_DISP_H_PULSE0_CONTROL_0, // 40B
78 DC_DISP_H_PULSE0_POSITION_A_0, // 40C
79 DC_DISP_H_PULSE0_POSITION_B_0, // 40D
80 DC_DISP_H_PULSE0_POSITION_C_0, // 40E
81 DC_DISP_H_PULSE0_POSITION_D_0, // 40F
82 DC_DISP_H_PULSE1_CONTROL_0, // 410
83 DC_DISP_H_PULSE1_POSITION_A_0, // 411
84 DC_DISP_H_PULSE1_POSITION_B_0, // 412
85 DC_DISP_H_PULSE1_POSITION_C_0, // 413
86 DC_DISP_H_PULSE1_POSITION_D_0, // 414
87 DC_DISP_H_PULSE2_CONTROL_0, // 415
88 DC_DISP_H_PULSE2_POSITION_A_0, // 416
89 DC_DISP_H_PULSE2_POSITION_B_0, // 417
90 DC_DISP_H_PULSE2_POSITION_C_0, // 418
91 DC_DISP_H_PULSE2_POSITION_D_0, // 419
92 DC_DISP_V_PULSE0_CONTROL_0, // 41A
93 DC_DISP_V_PULSE0_POSITION_A_0, // 41B
94 DC_DISP_V_PULSE0_POSITION_B_0, // 41C
95 DC_DISP_V_PULSE0_POSITION_C_0, // 41D
96 DC_DISP_V_PULSE1_CONTROL_0, // 41E
97 DC_DISP_V_PULSE1_POSITION_A_0, // 41F
98 DC_DISP_V_PULSE1_POSITION_B_0, // 420
99 DC_DISP_V_PULSE1_POSITION_C_0, // 421
100 DC_DISP_V_PULSE2_CONTROL_0, // 422
101 DC_DISP_V_PULSE2_POSITION_A_0, // 423
102 DC_DISP_V_PULSE3_CONTROL_0, // 424
103 DC_DISP_V_PULSE3_POSITION_A_0, // 425
104 DC_DISP_M0_CONTROL_0, // 426
105 DC_DISP_M1_CONTROL_0, // 427
106 DC_DISP_DI_CONTROL_0, // 428
107 DC_DISP_PP_CONTROL_0, // 429
108 DC_DISP_PP_SELECT_A_0, // 42A
109 DC_DISP_PP_SELECT_B_0, // 42B
110 DC_DISP_PP_SELECT_C_0, // 42C
111 DC_DISP_PP_SELECT_D_0, // 42D
112 DC_DISP_DISP_CLOCK_CONTROL_0, // 42E
113 DC_DISP_DISP_INTERFACE_CONTROL_0,//42F
114 DC_DISP_DISP_COLOR_CONTROL_0, // 430
115 DC_DISP_SHIFT_CLOCK_OPTIONS_0, // 431
116 DC_DISP_DATA_ENABLE_OPTIONS_0, // 432
117 DC_DISP_SERIAL_INTERFACE_OPTIONS_0, // 433
118 DC_DISP_LCD_SPI_OPTIONS_0, // 434
119 DC_DISP_BORDER_COLOR_0, // 435
120 DC_DISP_COLOR_KEY0_LOWER_0, // 436
121 DC_DISP_COLOR_KEY0_UPPER_0, // 437
122 DC_DISP_COLOR_KEY1_LOWER_0, // 438
123 DC_DISP_COLOR_KEY1_UPPER_0, // 439
126 DC_DISP_CURSOR_FOREGROUND_0, // 43C - IMPORTANT
127 DC_DISP_CURSOR_BACKGROUND_0, // 43D - IMPORTANT
128 DC_DISP_CURSOR_START_ADDR_0, // 43E - IMPORTANT
129 DC_DISP_CURSOR_START_ADDR_NS_0, // 43F - IMPORTANT
130 DC_DISP_CURSOR_POSITION_0, // 440 - IMPORTANT
131 DC_DISP_CURSOR_POSITION_NS_0, // 441 - IMPORTANT
132 DC_DISP_INIT_SEQ_CONTROL_0, // 442
133 DC_DISP_SPI_INIT_SEQ_DATA_A_0, // 443
134 DC_DISP_SPI_INIT_SEQ_DATA_B_0, // 444
135 DC_DISP_SPI_INIT_SEQ_DATA_C_0, // 445
136 DC_DISP_SPI_INIT_SEQ_DATA_D_0, // 446
138 DC_DISP_DC_MCCIF_FIFOCTRL_0 = 0x480,
139 DC_DISP_MCCIF_DISPLAY0A_HYST_0, // 481
140 DC_DISP_MCCIF_DISPLAY0B_HYST_0, // 482
141 DC_DISP_MCCIF_DISPLAY0C_HYST_0, // 483
142 DC_DISP_MCCIF_DISPLAY1B_HYST_0, // 484
144 DC_DISP_DAC_CRT_CTRL_0 = 0x4C0,
145 DC_DISP_DISP_MISC_CONTROL_0, // 4C1
147 DC_WINC_A_COLOR_PALETTE_0 = 0x500,
148 DC_WINC_A_PALETTE_COLOR_EXT_0 = 0x600,
149 DC_WIN_A_WIN_OPTIONS_0 = 0x700,
150 DC_WIN_A_BYTE_SWAP_0, // 701
151 DC_WIN_A_BUFFER_CONTROL_0, // 702
152 DC_WIN_A_COLOR_DEPTH_0, // 703
153 DC_WIN_A_POSITION_0, // 704
154 DC_WIN_A_SIZE_0, // 705 (TrimSlice 0x0300 0400)
155 DC_WIN_A_PRESCALED_SIZE_0,
156 DC_WIN_A_H_INITIAL_DDA_0,
157 DC_WIN_A_V_INITIAL_DDA_0,
158 DC_WIN_A_DDA_INCREMENT_0,
159 DC_WIN_A_LINE_STRIDE_0,
160 DC_WIN_A_BUF_STRIDE_0,
161 DC_WIN_A_BUFFER_ADDR_MODE_0,
162 DC_WIN_A_DV_CONTROL_0,
163 DC_WIN_A_BLEND_NOKEY_0,
165 DC_WINBUF_A_START_ADDR_0 = 0x800,
166 DC_WINBUF_A_START_ADDR_NS_0,
167 DC_WINBUF_A_ADDR_H_OFFSET_0,
168 DC_WINBUF_A_ADDR_H_OFFSET_NS_0,
169 DC_WINBUF_A_ADDR_V_OFFSET_0,
170 DC_WINBUF_A_ADDR_V_OFFSET_NS_0,