1 -------------------------------------------------------------------------------
3 -- Project: <Floating Point Unit Core>
5 -- Description: Serial multiplication entity for the multiplication unit
6 -------------------------------------------------------------------------------
8 -- 100101011010011100100
9 -- 110000111011100100000
10 -- 100000111011000101101
11 -- 100010111100101111001
12 -- 110000111011101101001
13 -- 010000001011101001010
14 -- 110100111001001100001
15 -- 110111010000001100111
16 -- 110110111110001011101
17 -- 101110110010111101000
18 -- 100000010111000000000
20 -- Author: Jidan Al-eryani
25 -- This source file may be used and distributed without
26 -- restriction provided that this copyright statement is not
27 -- removed from the file and that any derivative work contains
28 -- the original copyright notice and the associated disclaimer.
30 -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31 -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
34 -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
37 -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38 -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
39 -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
41 -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 -- POSSIBILITY OF SUCH DAMAGE.
46 use ieee.std_logic_1164.all;
47 use ieee.std_logic_unsigned.all;
48 use ieee.std_logic_arith.all;
56 fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
57 fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
58 signa_i : in std_logic;
59 signb_i : in std_logic;
60 start_i : in std_logic;
61 fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
62 sign_o : out std_logic;
63 ready_o : out std_logic
67 architecture rtl of serial_mul is
69 type t_state is (waiting,busy);
71 signal s_fract_o: std_logic_vector(47 downto 0);
73 signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
74 signal s_signa_i, s_signb_i, s_sign_o : std_logic;
75 signal s_start_i, s_ready_o : std_logic;
76 signal s_state : t_state;
77 signal s_count : integer range 0 to 23;
78 signal s_tem_prod : std_logic_vector(23 downto 0);
85 if rising_edge(clk_i) then
86 s_fracta_i <= fracta_i;
87 s_fractb_i <= fractb_i;
97 if rising_edge(clk_i) then
100 ready_o <= s_ready_o;
104 s_sign_o <= signa_i xor signb_i;
109 if rising_edge(clk_i) then
110 if s_start_i ='1' then
113 elsif s_count=23 then
117 elsif s_state=busy then
118 s_count <= s_count + 1;
126 g1: for i in 0 to 23 generate
127 s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
131 variable v_prod_shl : std_logic_vector(47 downto 0);
133 if rising_edge(clk_i) then
135 v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
137 s_fract_o <= v_prod_shl + s_fract_o;
139 s_fract_o <= v_prod_shl;