src/serial_mul.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: Serial multiplication entity for the multiplication unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_arith.all;
  49
  50 library work;
  51 use work.fpupack.all;
  52
  53 entity serial_mul is
  54         port(
  55                          clk_i                          : in std_logic;
  56                          fracta_i                       : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
  57                          fractb_i                       : in std_logic_vector(FRAC_WIDTH downto 0);
  58                          signa_i                        : in std_logic;
  59                          signb_i                        : in std_logic;
  60                          start_i                        : in std_logic;
  61                          fract_o                        : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
  62                          sign_o                         : out std_logic;
  63                          ready_o                        : out std_logic
  64                          );
  65 end serial_mul;
  66
  67 architecture rtl of serial_mul is
  68
  69 type t_state is (waiting,busy);
  70
  71 signal s_fract_o: std_logic_vector(47 downto 0);
  72
  73 signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
  74 signal s_signa_i, s_signb_i, s_sign_o : std_logic;
  75 signal s_start_i, s_ready_o : std_logic;
  76 signal s_state : t_state;
  77 signal s_count : integer range 0 to 23;
  78 signal s_tem_prod : std_logic_vector(23 downto 0);
  79
  80 begin
  81
  82 -- Input Register
  83 process(clk_i)
  84 begin
  85         if rising_edge(clk_i) then
  86                 s_fracta_i <= fracta_i;
  87                 s_fractb_i <= fractb_i;
  88                 s_signa_i<= signa_i;
  89                 s_signb_i<= signb_i;
  90                 s_start_i <= start_i;
  91         end if;
  92 end process;
  93
  94 -- Output Register
  95 process(clk_i)
  96 begin
  97         if rising_edge(clk_i) then
  98                 fract_o <= s_fract_o;
  99                 sign_o <= s_sign_o;
 100                 ready_o <= s_ready_o;
 101         end if;
 102 end process;
 103
 104 s_sign_o <= signa_i xor signb_i;
 105
 106 -- FSM
 107 process(clk_i)
 108 begin
 109         if rising_edge(clk_i) then
 110                 if s_start_i ='1' then
 111                         s_state <= busy;
 112                         s_count <= 0;
 113                 elsif s_count=23 then
 114                         s_state <= waiting;
 115                         s_ready_o <= '1';
 116                         s_count <=0;
 117                 elsif s_state=busy then
 118                         s_count <= s_count + 1;
 119                 else
 120                         s_state <= waiting;
 121                         s_ready_o <= '0';
 122                 end if;
 123         end if;
 124 end process;
 125
 126 g1: for i in 0 to 23 generate
 127         s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
 128 end generate;
 129
 130 process(clk_i)
 131 variable v_prod_shl : std_logic_vector(47 downto 0);
 132 begin
 133         if rising_edge(clk_i) then
 134                 if s_state=busy then
 135                         v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
 136                         if s_count /= 0 then
 137                                 s_fract_o <= v_prod_shl + s_fract_o;
 138                         else
 139                                 s_fract_o <= v_prod_shl;
 140                         end if;
 141                 end if;
 142         end if;
 143 end process;
 144
 145 end rtl;
 146