src/addsub_28.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: addition/subtraction entity for the addition/subtraction unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_misc.all;
  49 use IEEE.std_logic_arith.all;
  50
  51 library work;
  52 use work.fpupack.all;
  53
  54 entity addsub_28 is
  55         port(
  56                         clk_i                   : in std_logic;
  57                         fpu_op_i                : in std_logic;
  58                         fracta_i                : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
  59                         fractb_i                : in std_logic_vector(FRAC_WIDTH+4 downto 0);
  60                         signa_i                 : in std_logic;
  61                         signb_i                 : in std_logic;
  62                         fract_o                 : out std_logic_vector(FRAC_WIDTH+4 downto 0);
  63                         sign_o                  : out std_logic);
  64 end addsub_28;
  65
  66
  67 architecture rtl of addsub_28 is
  68
  69 signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
  70 signal s_fract_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
  71 signal s_signa_i, s_signb_i, s_sign_o : std_logic;
  72 signal s_fpu_op_i : std_logic;
  73
  74 signal fracta_lt_fractb : std_logic;
  75 signal s_addop: std_logic;
  76
  77 begin
  78
  79 -- Input Register
  80 --process(clk_i)
  81 --begin
  82 --      if rising_edge(clk_i) then
  83                 s_fracta_i <= fracta_i;
  84                 s_fractb_i <= fractb_i;
  85                 s_signa_i<= signa_i;
  86                 s_signb_i<= signb_i;
  87                 s_fpu_op_i <= fpu_op_i;
  88 --      end if;
  89 --end process;
  90
  91 -- Output Register
  92 process(clk_i)
  93 begin
  94         if rising_edge(clk_i) then
  95                 fract_o <= s_fract_o;
  96                 sign_o <= s_sign_o;
  97         end if;
  98 end process;
  99
 100 fracta_lt_fractb <= '1' when s_fracta_i > s_fractb_i else '0';
 101
 102 -- check if its a subtraction or an addition operation
 103 s_addop <= ((s_signa_i xor s_signb_i)and not (s_fpu_op_i)) or ((s_signa_i xnor s_signb_i)and (s_fpu_op_i));
 104
 105 -- sign of result
 106 s_sign_o <= '0' when s_fract_o = conv_std_logic_vector(0,28) and (s_signa_i and s_signb_i)='0' else
 107                                                                                 ((not s_signa_i) and ((not fracta_lt_fractb) and (fpu_op_i xor s_signb_i))) or
 108                                                                                 ((s_signa_i) and (fracta_lt_fractb or (fpu_op_i xor s_signb_i)));
 109
 110 -- add/substract
 111 process(s_fracta_i, s_fractb_i, s_addop, fracta_lt_fractb)
 112 begin
 113         if s_addop='0' then
 114                 s_fract_o <= s_fracta_i + s_fractb_i;
 115         else
 116                 if fracta_lt_fractb = '1' then
 117                         s_fract_o <= s_fracta_i - s_fractb_i;
 118                 else
 119                         s_fract_o <= s_fractb_i - s_fracta_i;
 120                 end if;
 121         end if;
 122 end process;
 123
 124
 125
 126
 127 end rtl;
 128