src/mul_24.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: multiplication entity for the multiplication unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48
  49 library work;
  50 use work.fpupack.all;
  51
  52 entity mul_24 is
  53         port(
  54                          clk_i                          : in std_logic;
  55                          fracta_i                       : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
  56                          fractb_i                       : in std_logic_vector(FRAC_WIDTH downto 0);
  57                          signa_i                        : in std_logic;
  58                          signb_i                        : in std_logic;
  59                          start_i                        : in std_logic;
  60                          fract_o                        : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
  61                          sign_o                         : out std_logic;
  62                          ready_o                        : out std_logic
  63                          );
  64 end mul_24;
  65
  66 architecture rtl of mul_24 is
  67
  68
  69
  70 signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH downto 0);
  71 signal s_signa_i, s_signb_i, s_sign_o : std_logic;
  72 signal s_fract_o: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
  73 signal s_start_i, s_ready_o : std_logic;
  74
  75 signal a_h, a_l, b_h, b_l : std_logic_vector(11 downto 0);
  76 signal a_h_h, a_h_l, b_h_h, b_h_l, a_l_h, a_l_l, b_l_h, b_l_l : std_logic_vector(5 downto 0);
  77
  78 type op_6 is array (7 downto 0) of std_logic_vector(5 downto 0);
  79 type prod_6 is array (3 downto 0) of op_6;
  80
  81 type prod_48 is array (4 downto 0) of std_logic_vector(47 downto 0);
  82 type sum_24 is array (3 downto 0) of std_logic_vector(23 downto 0);
  83
  84 type a is array (3 downto 0) of std_logic_vector(23 downto 0);
  85 type prod_24 is array (3 downto 0) of a;
  86
  87 signal prod : prod_6;
  88 signal sum : sum_24;
  89 signal prod_a_b : prod_48;
  90
  91 signal count : integer range 0 to 4;
  92
  93
  94 type t_state is (waiting,busy);
  95 signal s_state : t_state;
  96
  97 signal prod2 : prod_24;
  98 begin
  99
 100
 101 -- Input Register
 102 process(clk_i)
 103 begin
 104         if rising_edge(clk_i) then
 105                 s_fracta_i <= fracta_i;
 106                 s_fractb_i <= fractb_i;
 107                 s_signa_i<= signa_i;
 108                 s_signb_i<= signb_i;
 109                 s_start_i<=start_i;
 110         end if;
 111 end process;
 112
 113 -- Output Register
 114 --process(clk_i)
 115 --begin
 116 --      if rising_edge(clk_i) then
 117                 fract_o <= s_fract_o;
 118                 sign_o <= s_sign_o;
 119                 ready_o<=s_ready_o;
 120 --      end if;
 121 --end process;
 122
 123
 124 -- FSM
 125 process(clk_i)
 126 begin
 127         if rising_edge(clk_i) then
 128                 if s_start_i ='1' then
 129                         s_state <= busy;
 130                         count <= 0;
 131                 elsif count=4 and s_state=busy then
 132                         s_state <= waiting;
 133                         s_ready_o <= '1';
 134                         count <=0;
 135                 elsif s_state=busy then
 136                         count <= count + 1;
 137                 else
 138                         s_state <= waiting;
 139                         s_ready_o <= '0';
 140                 end if;
 141         end if;
 142 end process;
 143
 144 s_sign_o <= s_signa_i xor s_signb_i;
 145
 146 --"000000000000"
 147 -- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l
 148 -- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l
 149 a_h <= s_fracta_i(23 downto 12);
 150 a_l <= s_fracta_i(11 downto 0);
 151 b_h <= s_fractb_i(23 downto 12);
 152 b_l <= s_fractb_i(11 downto 0);
 153
 154
 155
 156 a_h_h <= a_h(11 downto 6);
 157 a_h_l <= a_h(5 downto 0);
 158 b_h_h <= b_h(11 downto 6);
 159 b_h_l <= b_h(5 downto 0);
 160
 161 a_l_h <= a_l(11 downto 6);
 162 a_l_l <= a_l(5 downto 0);
 163 b_l_h <= b_l(11 downto 6);
 164 b_l_l <= b_l(5 downto 0);
 165
 166
 167 prod(0)(0) <= a_h_h; prod(0)(1) <= b_h_h;
 168 prod(0)(2) <= a_h_h; prod(0)(3) <= b_h_l;
 169 prod(0)(4) <= a_h_l; prod(0)(5) <= b_h_h;
 170 prod(0)(6) <= a_h_l; prod(0)(7) <= b_h_l;
 171
 172
 173 prod(1)(0) <= a_h_h; prod(1)(1) <= b_l_h;
 174 prod(1)(2) <= a_h_h; prod(1)(3) <= b_l_l;
 175 prod(1)(4) <= a_h_l; prod(1)(5) <= b_l_h;
 176 prod(1)(6) <= a_h_l; prod(1)(7) <= b_l_l;
 177
 178 prod(2)(0) <= a_l_h; prod(2)(1) <= b_h_h;
 179 prod(2)(2) <= a_l_h; prod(2)(3) <= b_h_l;
 180 prod(2)(4) <= a_l_l; prod(2)(5) <= b_h_h;
 181 prod(2)(6) <= a_l_l; prod(2)(7) <= b_h_l;
 182
 183 prod(3)(0) <= a_l_h; prod(3)(1) <= b_l_h;
 184 prod(3)(2) <= a_l_h; prod(3)(3) <= b_l_l;
 185 prod(3)(4) <= a_l_l; prod(3)(5) <= b_l_h;
 186 prod(3)(6) <= a_l_l; prod(3)(7) <= b_l_l;
 187
 188
 189
 190 process(clk_i)
 191 begin
 192 if rising_edge(clk_i) then
 193         if count < 4 then
 194                 prod2(count)(0)  <= (prod(count)(0)*prod(count)(1))&"000000000000";
 195                 prod2(count)(1) <= "000000"&(prod(count)(2)*prod(count)(3))&"000000";
 196                 prod2(count)(2) <= "000000"&(prod(count)(4)*prod(count)(5))&"000000";
 197                 prod2(count)(3) <= "000000000000"&(prod(count)(6)*prod(count)(7));
 198         end if;
 199 end if;
 200 end process;
 201
 202
 203
 204 process(clk_i)
 205 begin
 206 if rising_edge(clk_i) then
 207         if count > 0 and s_state=busy then
 208                 sum(count-1) <= prod2(count-1)(0) + prod2(count-1)(1) + prod2(count-1)(2) + prod2(count-1)(3);
 209         end if;
 210 end if;
 211 end process;
 212
 213
 214
 215 -- Last stage
 216
 217
 218         prod_a_b(0) <= sum(0)&"000000000000000000000000";
 219         prod_a_b(1) <= "000000000000"&sum(1)&"000000000000";
 220         prod_a_b(2) <= "000000000000"&sum(2)&"000000000000";
 221         prod_a_b(3) <= "000000000000000000000000"&sum(3);
 222
 223         prod_a_b(4) <= prod_a_b(0) + prod_a_b(1) + prod_a_b(2) + prod_a_b(3);
 224
 225         s_fract_o <= prod_a_b(4);
 226
 227
 228
 229 end rtl;
 230