src/post_norm_div.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: post-normalization entity for the division unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_misc.all;
  49
  50 library work;
  51 use work.fpupack.all;
  52
  53
  54 entity post_norm_div is
  55         port(
  56                          clk_i                          : in std_logic;
  57                          opa_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
  58                          opb_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
  59                          qutnt_i                        : in std_logic_vector(FRAC_WIDTH+3 downto 0);
  60                          rmndr_i                        : in std_logic_vector(FRAC_WIDTH+3 downto 0);
  61                          exp_10_i                       : in std_logic_vector(EXP_WIDTH+1 downto 0);
  62                          sign_i                         : in std_logic;
  63                          rmode_i                        : in std_logic_vector(1 downto 0);
  64                          output_o                       : out std_logic_vector(FP_WIDTH-1 downto 0);
  65                          ine_o                          : out std_logic
  66                 );
  67 end post_norm_div;
  68
  69 architecture rtl of post_norm_div is
  70
  71
  72 -- input&output register signals
  73 signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
  74 signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
  75 signal s_qutnt_i, s_rmndr_i : std_logic_vector(FRAC_WIDTH+3 downto 0);
  76 signal s_r_zeros        : std_logic_vector(5 downto 0);
  77 signal s_exp_10_i                       : std_logic_vector(EXP_WIDTH+1 downto 0);
  78 signal s_sign_i                         : std_logic;
  79 signal s_rmode_i                        : std_logic_vector(1 downto 0);
  80 signal s_output_o                        : std_logic_vector(FP_WIDTH-1 downto 0);
  81 signal s_ine_o, s_overflow : std_logic;
  82
  83 signal s_opa_dn, s_opb_dn : std_logic;
  84 signal s_qutdn : std_logic;
  85
  86 signal s_exp_10b : std_logic_vector(9 downto 0);
  87 signal s_shr1, s_shl1 : std_logic_vector(5 downto 0);
  88 signal s_shr2 : std_logic;
  89 signal s_expo1, s_expo2, s_expo3 : std_logic_vector(8 downto 0);
  90 signal s_fraco1 : std_logic_vector(26 downto 0);
  91 signal s_frac_rnd, s_fraco2 : std_logic_vector(24 downto 0);
  92 signal s_guard, s_round, s_sticky, s_roundup : std_logic;
  93 signal s_lost : std_logic;
  94
  95 signal s_op_0, s_opab_0, s_opb_0 : std_logic;
  96 signal s_infa, s_infb : std_logic;
  97 signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic;
  98 signal s_inf_result: std_logic;
  99
 100 begin
 101
 102         -- Input Register
 103         process(clk_i)
 104         begin
 105                 if rising_edge(clk_i) then
 106                         s_opa_i <= opa_i;
 107                         s_opb_i <= opb_i;
 108                         s_expa <= opa_i(30 downto 23);
 109                         s_expb <= opb_i(30 downto 23);
 110                         s_qutnt_i <= qutnt_i;
 111                         s_rmndr_i <= rmndr_i;
 112                         s_exp_10_i <= exp_10_i;
 113                         s_sign_i <= sign_i;
 114                         s_rmode_i <= rmode_i;
 115                 end if;
 116         end process;
 117
 118         -- Output Register
 119         process(clk_i)
 120         begin
 121                 if rising_edge(clk_i) then
 122                         output_o <= s_output_o;
 123                         ine_o   <= s_ine_o;
 124                 end if;
 125         end process;
 126
 127     -- qutnt_i
 128     -- 26 25                    3
 129     -- |  |                     |
 130     -- h  fffffffffffffffffffffff grs
 131
 132         --*** Stage 1 ****
 133         -- figure out the exponent and howmuch the fraction has to be shiftd right/left
 134
 135         s_opa_dn <= '1' when or_reduce(s_expa)='0' and or_reduce(opa_i(22 downto 0))='1' else '0';
 136         s_opb_dn <= '1' when or_reduce(s_expb)='0' and or_reduce(opb_i(22 downto 0))='1' else '0';
 137
 138         s_qutdn <= not s_qutnt_i(26);
 139
 140
 141         s_exp_10b <= s_exp_10_i - ("000000000"&s_qutdn);
 142
 143
 144
 145         process(clk_i)
 146                 variable v_shr, v_shl : std_logic_vector(9 downto 0);
 147         begin
 148                 if rising_edge(clk_i) then
 149                 if s_exp_10b(9)='1' or s_exp_10b="0000000000" then
 150                         v_shr := ("0000000001" - s_exp_10b) - s_qutdn;
 151                         v_shl := (others =>'0');
 152                         s_expo1 <= "000000001";
 153                 elsif s_exp_10b(8)='1' then
 154                         v_shr := (others =>'0');
 155                         v_shl := (others =>'0');
 156                         s_expo1 <= s_exp_10b(8 downto 0);
 157                 else
 158                         v_shr := (others =>'0');
 159                         v_shl :=  "000000000"& s_qutdn;
 160                         s_expo1 <= s_exp_10b(8 downto 0);
 161                 end if;
 162                 if  v_shr(6)='1' then
 163                         s_shr1 <= "111111";
 164                 else
 165                         s_shr1 <= v_shr(5 downto 0);
 166                 end if;
 167                 s_shl1 <= v_shl(5 downto 0);
 168                 end if;
 169         end process;
 170
 171
 172         -- *** Stage 2 ***
 173         -- Shifting the fraction and rounding
 174
 175
 176         -- shift the fraction
 177         process(clk_i)
 178         begin
 179                 if rising_edge(clk_i) then
 180                         if s_shr1 /= "000000" then
 181                                 s_fraco1 <= shr(s_qutnt_i, s_shr1);
 182                         else
 183                                 s_fraco1 <= shl(s_qutnt_i, s_shl1);
 184                         end if;
 185                 end if;
 186         end process;
 187
 188         s_expo2 <= s_expo1 - "000000001" when s_fraco1(26)='0' else s_expo1;
 189
 190
 191         s_r_zeros <= count_r_zeros(s_qutnt_i);
 192
 193
 194         s_lost <= '1' when (s_shr1+("00000"&s_shr2)) > s_r_zeros else '0';
 195
 196         -- ***Stage 3***
 197         -- Rounding
 198
 199         s_guard <= s_fraco1(2);
 200         s_round <= s_fraco1(1);
 201         s_sticky <= s_fraco1(0) or or_reduce(s_rmndr_i);
 202
 203         s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
 204                                  ( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
 205                                  ( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
 206                                  '0'; -- round to zero(truncate = no rounding)
 207
 208
 209         s_frac_rnd <= ("0"&s_fraco1(26 downto 3)) + '1' when s_roundup='1' else "0"&s_fraco1(26 downto 3);
 210         s_shr2 <= s_frac_rnd(24);
 211
 212         process(clk_i)
 213         begin
 214                 if rising_edge(clk_i) then
 215                         if s_shr2='1' then
 216                                 s_expo3 <= s_expo2 + "1";
 217                                 s_fraco2 <= "0"&s_frac_rnd(24 downto 1);
 218                         else
 219                                 s_expo3 <= s_expo2;
 220                                 s_fraco2 <= s_frac_rnd;
 221                         end if;
 222                 end if;
 223         end process;
 224
 225
 226         ---
 227
 228         ---***Stage 4****
 229         -- Output
 230
 231         s_op_0 <= not ( or_reduce(s_opa_i(30 downto 0)) and or_reduce(s_opb_i(30 downto 0)) );
 232         s_opab_0 <= not ( or_reduce(s_opa_i(30 downto 0)) or or_reduce(s_opb_i(30 downto 0)) );
 233         s_opb_0 <= not or_reduce(s_opb_i(30 downto 0));
 234
 235         s_infa <= '1' when s_expa="11111111"  else '0';
 236         s_infb <= '1' when s_expb="11111111"  else '0';
 237
 238         s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
 239         s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
 240         s_nan_in <= '1' when s_nan_a='1' or  s_nan_b='1' else '0';
 241         s_nan_op <= '1' when (s_infa and s_infb)='1' or s_opab_0='1' else '0';-- 0 / 0, inf / inf
 242
 243         s_inf_result <= '1' when (and_reduce(s_expo3(7 downto 0)) or s_expo3(8))='1' or s_opb_0='1' else '0';
 244
 245         s_overflow <= '1' when s_inf_result='1'  and (s_infa or s_infb)='0' and s_opb_0='0' else '0';
 246
 247         s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_fraco1(2 downto 0)) or s_overflow or or_reduce(s_rmndr_i))='1' else '0';
 248
 249         process(s_sign_i, s_expo3, s_fraco2, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_inf_result, s_op_0)
 250         begin
 251                 if (s_nan_in or s_nan_op)='1' then
 252                         s_output_o <= '1' & QNAN;
 253                 elsif (s_infa or s_infb)='1' or s_overflow='1' or s_inf_result='1' then
 254                                 s_output_o <= s_sign_i & INF;
 255                 elsif s_op_0='1' then
 256                                 s_output_o <= s_sign_i & ZERO_VECTOR;
 257                 else
 258                                 s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_fraco2(22 downto 0);
 259                 end if;
 260         end process;
 261
 262 end rtl;