src/post_norm_mul.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: post-normalization entity for the multiplication unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_misc.all;
  49
  50 library work;
  51 use work.fpupack.all;
  52
  53 entity post_norm_mul is
  54         port(
  55                          clk_i                          : in std_logic;
  56                          opa_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
  57                          opb_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
  58                          exp_10_i                       : in std_logic_vector(EXP_WIDTH+1 downto 0);
  59                          fract_48_i                     : in std_logic_vector(2*FRAC_WIDTH+1 downto 0); -- hidden(1) & fraction(23)
  60                          sign_i                         : in std_logic;
  61                          rmode_i                        : in std_logic_vector(1 downto 0);
  62                          output_o                       : out std_logic_vector(FP_WIDTH-1 downto 0);
  63                          ine_o                          : out std_logic
  64                 );
  65 end post_norm_mul;
  66
  67 architecture rtl of post_norm_mul is
  68
  69 signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
  70 signal s_exp_10_i : std_logic_vector(EXP_WIDTH+1 downto 0);
  71 signal s_fract_48_i : std_logic_vector(2*FRAC_WIDTH+1 downto 0);
  72 signal s_sign_i                         : std_logic;
  73 signal s_output_o                        : std_logic_vector(FP_WIDTH-1 downto 0);
  74 signal s_ine_o, s_overflow : std_logic;
  75 signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
  76 signal s_rmode_i                        : std_logic_vector(1 downto 0);
  77
  78 signal s_zeros  : std_logic_vector(5 downto 0);
  79 signal s_carry   : std_logic;
  80 signal s_shr2, s_shl2 : std_logic_vector(5 downto 0);
  81 signal s_expo1, s_expo2b : std_logic_vector(8 downto 0);
  82 signal s_exp_10a, s_exp_10b : std_logic_vector(9 downto 0);
  83 signal s_frac2a : std_logic_vector(47 downto 0);
  84
  85 signal s_sticky, s_guard, s_round : std_logic;
  86 signal s_roundup : std_logic;
  87 signal s_frac_rnd, s_frac3 : std_logic_vector(24 downto 0);
  88 signal s_shr3 : std_logic;
  89 signal s_r_zeros : std_logic_vector(5 downto 0);
  90 signal s_lost : std_logic;
  91 signal s_op_0 : std_logic;
  92 signal s_expo3 : std_logic_vector(8 downto 0);
  93
  94 signal s_infa, s_infb : std_logic;
  95 signal s_nan_in, s_nan_op, s_nan_a, s_nan_b : std_logic;
  96
  97 begin
  98
  99         -- Input Register
 100         process(clk_i)
 101         begin
 102                 if rising_edge(clk_i) then
 103                         s_opa_i <= opa_i;
 104                         s_opb_i <= opb_i;
 105                         s_expa <= opa_i(30 downto 23);
 106                         s_expb <= opb_i(30 downto 23);
 107                         s_exp_10_i <= exp_10_i;
 108                         s_fract_48_i <= fract_48_i;
 109                         s_sign_i <= sign_i;
 110                         s_rmode_i <= rmode_i;
 111                 end if;
 112         end process;
 113
 114         -- Output Register
 115         process(clk_i)
 116         begin
 117                 if rising_edge(clk_i) then
 118                         output_o <= s_output_o;
 119                         ine_o   <= s_ine_o;
 120                 end if;
 121         end process;
 122
 123         --*** Stage 1 ****
 124         -- figure out the exponent and howmuch the fraction has to be shiftd right/left
 125
 126         s_carry <= s_fract_48_i(47);
 127
 128         process(clk_i)
 129         begin
 130                 if rising_edge(clk_i) then
 131                         if s_fract_48_i(47)='0' then
 132                                 s_zeros <= count_l_zeros(s_fract_48_i(46 downto 1));
 133                         else
 134                                 s_zeros <= "000000";
 135                         end if;
 136                         s_r_zeros <= count_r_zeros(s_fract_48_i);
 137                 end if;
 138         end process;
 139
 140         s_exp_10a <= s_exp_10_i + ("000000000"&s_carry);
 141         s_exp_10b <= s_exp_10a - ("0000"&s_zeros);
 142
 143         process(clk_i)
 144                 variable v_shr1, v_shl1 : std_logic_vector(9 downto 0);
 145         begin
 146         if rising_edge(clk_i) then
 147                 if s_exp_10a(9)='1' or s_exp_10a="0000000000" then
 148                         v_shr1 := "0000000001" - s_exp_10a + ("000000000"&s_carry);
 149                         v_shl1 := (others =>'0');
 150                         s_expo1 <= "000000001";
 151                 else
 152                         if s_exp_10b(9)='1' or s_exp_10b="0000000000" then
 153                                 v_shr1 := (others =>'0');
 154                                 v_shl1 := ("0000"&s_zeros) - s_exp_10a;
 155                                 s_expo1 <= "000000001";
 156                         elsif s_exp_10b(8)='1' then
 157                                 v_shr1 := (others =>'0');
 158                                 v_shl1 := (others =>'0');
 159                                 s_expo1 <= "011111111";
 160                         else
 161                                 v_shr1 := ("000000000"&s_carry);
 162                                 v_shl1 := ("0000"&s_zeros);
 163                                 s_expo1 <= s_exp_10b(8 downto 0);
 164                         end if;
 165                 end if;
 166                 if  v_shr1(6)='1' then --"110000" = 48; maximal shift-right postions
 167                 s_shr2 <= "111111";
 168             else
 169                         s_shr2 <= v_shr1(5 downto 0);
 170                 end if;
 171                 s_shl2 <= v_shl1(5 downto 0);
 172                 end if;
 173         end process;
 174
 175
 176         -- *** Stage 2 ***
 177         -- Shifting the fraction and rounding
 178
 179
 180         -- shift the fraction
 181         process(clk_i)
 182         begin
 183                 if rising_edge(clk_i) then
 184                         if s_shr2 /= "000000" then
 185                                 s_frac2a <= shr(s_fract_48_i, s_shr2);
 186                         else
 187                                 s_frac2a <= shl(s_fract_48_i, s_shl2);
 188                         end if;
 189                 end if;
 190         end process;
 191
 192         s_expo2b <= s_expo1 - "000000001" when s_frac2a(46)='0' else s_expo1;
 193
 194
 195
 196         -- signals if precision was last during the right-shift above
 197         s_lost <= '1' when (s_shr2+("00000"&s_shr3)) > s_r_zeros else '0';
 198
 199
 200         -- ***Stage 3***
 201         -- Rounding
 202
 203         --                                                                 23
 204         --                                                                      |
 205         --                      xx00000000000000000000000grsxxxxxxxxxxxxxxxxxxxx
 206         -- guard bit: s_frac2a(23) (LSB of output)
 207     -- round bit: s_frac2a(22)
 208         s_guard <= s_frac2a(22);
 209         s_round <= s_frac2a(21);
 210         s_sticky <= or_reduce(s_frac2a(20 downto 0)) or s_lost;
 211
 212         s_roundup <= s_guard and ((s_round or s_sticky)or s_frac2a(23)) when s_rmode_i="00" else -- round to nearset even
 213                                  ( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
 214                                  ( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
 215                                  '0'; -- round to zero(truncate = no rounding)
 216
 217
 218         process(clk_i)
 219         begin
 220         if rising_edge(clk_i) then
 221                 if s_roundup='1' then
 222                         s_frac_rnd <= (s_frac2a(47 downto 23)) + "1";
 223                 else
 224                         s_frac_rnd <= (s_frac2a(47 downto 23));
 225                 end if;
 226         end if;
 227         end process;
 228
 229         s_shr3 <= s_frac_rnd(24);
 230
 231
 232
 233         s_expo3 <= s_expo2b + '1' when s_shr3='1' and s_expo2b /= "011111111" else s_expo2b;
 234         s_frac3 <= ("0"&s_frac_rnd(24 downto 1)) when s_shr3='1' and s_expo2b /= "011111111" else s_frac_rnd;
 235
 236
 237         ---***Stage 4****
 238         -- Output
 239
 240         s_op_0 <= not ( or_reduce(s_opa_i(30 downto 0)) and or_reduce(s_opb_i(30 downto 0)) );
 241
 242         s_infa <= '1' when s_expa="11111111"  else '0';
 243         s_infb <= '1' when s_expb="11111111"  else '0';
 244
 245         s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
 246         s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
 247         s_nan_in <= '1' when s_nan_a='1' or  s_nan_b='1' else '0';
 248         s_nan_op <= '1' when (s_infa or s_infb)='1' and s_op_0='1' else '0';-- 0 * inf = nan
 249
 250
 251         s_overflow <= '1' when s_expo3 = "011111111" and (s_infa or s_infb)='0' else '0';
 252
 253         s_ine_o <= '1' when s_op_0='0' and (s_lost or or_reduce(s_frac2a(22 downto 0)) or s_overflow)='1' else '0';
 254
 255         process(s_sign_i, s_expo3, s_frac3, s_nan_in, s_nan_op, s_infa, s_infb, s_overflow, s_r_zeros)
 256         begin
 257                 if (s_nan_in or s_nan_op)='1' then
 258                         s_output_o <= s_sign_i & QNAN;
 259                 elsif (s_infa or s_infb)='1' or s_overflow='1' then
 260                                 s_output_o <= s_sign_i & INF;
 261                 elsif s_r_zeros=48 then
 262                                 s_output_o <= s_sign_i & ZERO_VECTOR;
 263                 else
 264                                 s_output_o <= s_sign_i & s_expo3(7 downto 0) & s_frac3(22 downto 0);
 265
 266                 end if;
 267         end process;
 268
 269 end rtl;