src/post_norm_sqrt.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: post-normalization entity for the square-root unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_misc.all;
  49
  50 library work;
  51 use work.fpupack.all;
  52
  53 entity post_norm_sqrt is
  54         port(
  55                         clk_i                   : in std_logic;
  56                         opa_i                   : in std_logic_vector(FP_WIDTH-1 downto 0);
  57                         fract_26_i              : in std_logic_vector(FRAC_WIDTH+2 downto 0);   -- hidden(1) & fraction(11)
  58                         exp_i                   : in std_logic_vector(EXP_WIDTH-1 downto 0);
  59                         ine_i                   : in std_logic;
  60                         rmode_i                 : in std_logic_vector(1 downto 0);
  61                         output_o                : out std_logic_vector(FP_WIDTH-1 downto 0);
  62                         ine_o                   : out std_logic
  63                 );
  64 end post_norm_sqrt;
  65
  66 architecture rtl of post_norm_sqrt is
  67
  68 signal s_expa, s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
  69 signal s_fract_26_i : std_logic_vector(FRAC_WIDTH+2 downto 0);
  70 signal s_ine_i          : std_logic;
  71 signal s_rmode_i                        : std_logic_vector(1 downto 0);
  72 signal s_output_o       : std_logic_vector(FP_WIDTH-1 downto 0);
  73 signal s_sign_i : std_logic;
  74 signal s_opa_i : std_logic_vector(FP_WIDTH-1 downto 0);
  75 signal s_ine_o : std_logic;
  76
  77 signal s_expo : std_logic_vector(EXP_WIDTH-1 downto 0);
  78 signal s_fraco1 : std_logic_vector(FRAC_WIDTH+2 downto 0);
  79
  80 signal s_guard, s_round, s_sticky, s_roundup : std_logic;
  81 signal s_frac_rnd : std_logic_vector(FRAC_WIDTH downto 0);
  82
  83
  84 signal s_infa : std_logic;
  85 signal s_nan_op, s_nan_a: std_logic;
  86
  87 begin
  88
  89         -- Input Register
  90         process(clk_i)
  91         begin
  92                 if rising_edge(clk_i) then
  93                         s_opa_i <= opa_i;
  94                         s_expa <= opa_i(30 downto 23);
  95                         s_sign_i <= opa_i(31);
  96                         s_fract_26_i <= fract_26_i;
  97                         s_ine_i <= ine_i;
  98                         s_exp_i <= exp_i;
  99                         s_rmode_i <= rmode_i;
 100                 end if;
 101         end process;
 102
 103         -- Output Register
 104         process(clk_i)
 105         begin
 106                 if rising_edge(clk_i) then
 107                         output_o <= s_output_o;
 108                         ine_o <= s_ine_o;
 109                 end if;
 110         end process;
 111
 112
 113         -- *** Stage 1 ***
 114
 115         s_expo <= s_exp_i;
 116
 117         s_fraco1 <= s_fract_26_i;
 118
 119
 120         -- ***Stage 2***
 121         -- Rounding
 122
 123         s_guard <= s_fraco1(1);
 124         s_round <= s_fraco1(0);
 125         s_sticky <= s_ine_i;
 126
 127         s_roundup <= s_guard and ((s_round or s_sticky)or s_fraco1(3)) when s_rmode_i="00" else -- round to nearset even
 128                                  ( s_guard or s_round or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
 129                                  ( s_guard or s_round or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
 130                                  '0'; -- round to zero(truncate = no rounding)
 131
 132         process(clk_i)
 133         begin
 134         if rising_edge(clk_i) then
 135                 if s_roundup='1' then
 136                         s_frac_rnd <= s_fraco1(25 downto 2) + '1';
 137                 else
 138                         s_frac_rnd <= s_fraco1(25 downto 2);
 139                 end if;
 140         end if;
 141         end process;
 142
 143
 144
 145         -- ***Stage 3***
 146         -- Output
 147
 148         s_infa <= '1' when s_expa="11111111"  else '0';
 149         s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
 150         s_nan_op <= '1' when s_sign_i='1' and or_reduce(s_opa_i(30 downto 0))='1' else '0'; -- sqrt(-x) = NaN
 151
 152         s_ine_o <= '1' when s_ine_i='1' and (s_infa or s_nan_a or s_nan_op)='0' else '0';
 153
 154         process( s_nan_a, s_nan_op, s_infa, s_sign_i, s_expo, s_frac_rnd)
 155         begin
 156                 if (s_nan_a or s_nan_op)='1' then
 157                         s_output_o <= s_sign_i & QNAN;
 158                 elsif s_infa ='1'  then
 159                                 s_output_o <= s_sign_i & INF;
 160                 else
 161                                 s_output_o <= s_sign_i & s_expo & s_frac_rnd(22 downto 0);
 162
 163                 end if;
 164         end process;
 165
 166 end rtl;