src/pre_norm_mul.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: pre-normalization entity for the multiplication unit
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee ;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.std_logic_misc.all;
  49
  50 library work;
  51 use work.fpupack.all;
  52
  53 entity pre_norm_mul is
  54         port(
  55                          clk_i            : in std_logic;
  56                          opa_i                  : in std_logic_vector(FP_WIDTH-1 downto 0);
  57                          opb_i                  : in std_logic_vector(FP_WIDTH-1 downto 0);
  58                          exp_10_o                       : out std_logic_vector(EXP_WIDTH+1 downto 0);
  59                          fracta_24_o            : out std_logic_vector(FRAC_WIDTH downto 0);    -- hidden(1) & fraction(23)
  60                          fractb_24_o            : out std_logic_vector(FRAC_WIDTH downto 0)
  61                 );
  62 end pre_norm_mul;
  63
  64 architecture rtl of pre_norm_mul is
  65
  66 signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
  67 signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
  68 signal s_exp_10_o, s_expa_in, s_expb_in : std_logic_vector(EXP_WIDTH+1 downto 0);
  69
  70 signal s_opa_dn, s_opb_dn : std_logic;
  71
  72 begin
  73
  74
  75                 s_expa <= opa_i(30 downto 23);
  76                 s_expb <= opb_i(30 downto 23);
  77                 s_fracta <= opa_i(22 downto 0);
  78                 s_fractb <= opb_i(22 downto 0);
  79
  80         -- Output Register
  81         process(clk_i)
  82         begin
  83                 if rising_edge(clk_i) then
  84                         exp_10_o <= s_exp_10_o;
  85                 end if;
  86         end process;
  87
  88         -- opa or opb is denormalized
  89         s_opa_dn <= not or_reduce(s_expa);
  90         s_opb_dn <= not or_reduce(s_expb);
  91
  92
  93         fracta_24_o <= not(s_opa_dn) & s_fracta;
  94         fractb_24_o <= not(s_opb_dn) & s_fractb;
  95
  96         s_expa_in <= ("00"&s_expa) + ("000000000"&s_opa_dn);
  97         s_expb_in <= ("00"&s_expb) + ("000000000"&s_opb_dn);
  98
  99
 100
 101         s_exp_10_o <= s_expa_in + s_expb_in - "0001111111";
 102
 103
 104
 105 end rtl;