src/test_bench/tb_fpu.vhd

   1 -------------------------------------------------------------------------------
   2 --
   3 -- Project:     <Floating Point Unit Core>
   4 --
   5 -- Description: test bench for the FPU core
   6 -------------------------------------------------------------------------------
   7 --
   8 --                              100101011010011100100
   9 --                              110000111011100100000
  10 --                              100000111011000101101
  11 --                              100010111100101111001
  12 --                              110000111011101101001
  13 --                              010000001011101001010
  14 --                              110100111001001100001
  15 --                              110111010000001100111
  16 --                              110110111110001011101
  17 --                              101110110010111101000
  18 --                              100000010111000000000
  19 --
  20 --      Author:          Jidan Al-eryani
  21 --      E-mail:          [email protected]
  22 --
  23 --  Copyright (C) 2006
  24 --
  25 --      This source file may be used and distributed without
  26 --      restriction provided that this copyright statement is not
  27 --      removed from the file and that any derivative work contains
  28 --      the original copyright notice and the associated disclaimer.
  29 --
  30 --              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
  31 --      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  32 --      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  33 --      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
  34 --      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  35 --      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 --      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  37 --      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  38 --      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  39 --      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  40 --      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  41 --      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42 --      POSSIBILITY OF SUCH DAMAGE.
  43 --
  44
  45 library ieee;
  46 use ieee.std_logic_1164.all;
  47 use ieee.std_logic_unsigned.all;
  48 use ieee.math_real.all;
  49 use ieee.std_logic_arith.all;
  50 use ieee.std_logic_misc.all;
  51 use std.textio.all;
  52 use work.txt_util.all;
  53
  54         -- fpu operations (fpu_op_i):
  55                 -- ========================
  56                 -- 000 = add,
  57                 -- 001 = substract,
  58                 -- 010 = multiply,
  59                 -- 011 = divide,
  60                 -- 100 = square root
  61                 -- 101 = unused
  62                 -- 110 = unused
  63                 -- 111 = unused
  64
  65         -- Rounding Mode:
  66         -- ==============
  67         -- 00 = round to nearest even(default),
  68         -- 01 = round to zero,
  69         -- 10 = round up,
  70         -- 11 = round down
  71
  72
  73 entity tb_fpu is
  74 end tb_fpu;
  75
  76 architecture rtl of tb_fpu is
  77
  78 component fpu
  79     port (
  80         clk_i           : in std_logic;
  81         opa_i           : in std_logic_vector(31 downto 0);
  82         opb_i           : in std_logic_vector(31 downto 0);
  83         fpu_op_i                : in std_logic_vector(2 downto 0);
  84         rmode_i                 : in std_logic_vector(1 downto 0);
  85         output_o        : out std_logic_vector(31 downto 0);
  86                 ine_o                   : out std_logic;
  87         overflow_o      : out std_logic;
  88         underflow_o     : out std_logic;
  89         div_zero_o      : out std_logic;
  90         inf_o                   : out std_logic;
  91         zero_o                  : out std_logic;
  92         qnan_o                  : out std_logic;
  93         snan_o                  : out std_logic;
  94         start_i                 : in  std_logic;
  95         ready_o                 : out std_logic
  96         );
  97 end component;
  98
  99
 100 signal clk_i : std_logic:= '1';
 101 signal opa_i, opb_i : std_logic_vector(31 downto 0);
 102 signal fpu_op_i         : std_logic_vector(2 downto 0);
 103 signal rmode_i : std_logic_vector(1 downto 0);
 104 signal output_o : std_logic_vector(31 downto 0);
 105 signal start_i, ready_o : std_logic ;
 106 signal ine_o, overflow_o, underflow_o, div_zero_o, inf_o, zero_o, qnan_o, snan_o: std_logic;
 107
 108
 109
 110 signal slv_out : std_logic_vector(31 downto 0);
 111
 112 constant CLK_PERIOD :time := 10 ns; -- period of clk period
 113
 114
 115 begin
 116
 117     -- instantiate fpu
 118     i_fpu: fpu port map (
 119                         clk_i => clk_i,
 120                         opa_i => opa_i,
 121                         opb_i => opb_i,
 122                         fpu_op_i =>     fpu_op_i,
 123                         rmode_i => rmode_i,
 124                         output_o => output_o,
 125                         ine_o => ine_o,
 126                         overflow_o => overflow_o,
 127                         underflow_o => underflow_o,
 128                 div_zero_o => div_zero_o,
 129                 inf_o => inf_o,
 130                 zero_o => zero_o,
 131                 qnan_o => qnan_o,
 132                 snan_o => snan_o,
 133                 start_i => start_i,
 134                 ready_o => ready_o);
 135
 136
 137     ---------------------------------------------------------------------------
 138     -- toggle clock
 139     ---------------------------------------------------------------------------
 140     clk_i <= not(clk_i) after 5 ns;
 141
 142
 143     verify : process
 144                 --The operands and results are in Hex format. The test vectors must be placed in a strict order for the verfication to work.
 145                 file testcases_file: TEXT open read_mode is "testcases.txt"; --Name of the file containing the test cases.
 146
 147                 variable file_line: line;
 148                 variable str_in: string(8 downto 1);
 149                 variable str_fpu_op: string(3 downto 1);
 150                 variable str_rmode: string(2 downto 1);
 151     begin
 152
 153
 154                 ---------------------------------------------------------------------------------------------------------------------------------------------------
 155                 ---------------------------------------------------SoftFloat test vectors (10000 test cases for each operation) --------------------------------------------------------------------
 156                 start_i <= '0';
 157                 while not endfile(testcases_file) loop
 158
 159                         wait for CLK_PERIOD; start_i <= '1';
 160
 161                         str_read(testcases_file,str_in);
 162                         opa_i <= strhex_to_slv(str_in);
 163
 164                         str_read(testcases_file,str_in);
 165                         opb_i <= strhex_to_slv(str_in);
 166
 167                         str_read(testcases_file,str_fpu_op);
 168                         fpu_op_i <= to_std_logic_vector(str_fpu_op);
 169
 170                         str_read(testcases_file,str_rmode);
 171                         rmode_i <= to_std_logic_vector(str_rmode);
 172
 173                         str_read(testcases_file,str_in);
 174                         slv_out <= strhex_to_slv(str_in);
 175
 176                         wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 177
 178                         assert output_o = slv_out
 179                         report "Error!!!"
 180                         severity failure;
 181                         str_read(testcases_file,str_in);
 182
 183                 end loop;
 184
 185                 -------- Boundary values-----
 186
 187                 start_i <= '0';
 188                 --                seeeeeeeefffffffffffffffffffffff
 189                 --infinity
 190                 wait for CLK_PERIOD; start_i <= '1';
 191                 opa_i <= "01111111011111111111111111111111";
 192                 opb_i <= "01111111011111111111111111111111";
 193                 fpu_op_i <= "000";
 194                 rmode_i <= "00";
 195                 wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 196                 assert output_o="01111111100000000000000000000000"
 197                 report "Error!!!"
 198                 severity failure;
 199
 200                 --                seeeeeeeefffffffffffffffffffffff
 201                 -- 1 x1.001 - 1x1.000 = 0x0.001
 202                 wait for CLK_PERIOD; start_i <= '1';
 203                 opa_i <= "00000000100100000000000000000000";
 204                 opb_i <= "10000000100000000000000000000000";
 205                 fpu_op_i <= "000";
 206                 rmode_i <= "00";
 207                 wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 208                 assert output_o="00000000000100000000000000000000"
 209                 report "Error!!!"
 210                 severity failure;
 211
 212                 --                seeeeeeeefffffffffffffffffffffff
 213                 -- 10 x 1.0001 - 10 x 1.0000 =
 214                 wait for CLK_PERIOD; start_i <= '1';
 215                 opa_i <= "00000001000010000000000000000000";
 216                 opb_i <= "10000001000000000000000000000000";
 217                 fpu_op_i <= "000";
 218                 rmode_i <= "00";
 219                 wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 220                 assert output_o="00000000000100000000000000000000"
 221                 report "Error!!!"
 222                 severity failure;
 223
 224
 225                 --                seeeeeeeefffffffffffffffffffffff
 226                 -- -0 -0 = -0
 227                 wait for CLK_PERIOD; start_i <= '1';
 228                 opa_i <= "10000000000000000000000000000000";
 229                 opb_i <= "10000000000000000000000000000000";
 230                 fpu_op_i <= "000";
 231                 rmode_i <= "00";
 232                 wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 233                 assert output_o="10000000000000000000000000000000"
 234                 report "Error!!!"
 235                 severity failure;
 236
 237                 --                seeeeeeeefffffffffffffffffffffff
 238                 -- 0 + x = x
 239                 wait for CLK_PERIOD; start_i <= '1';
 240                 opa_i <= "00000000000000000000000000000000";
 241                 opb_i <= "01000010001000001000000000100000";
 242                 fpu_op_i <= "000";
 243                 rmode_i <= "00";
 244                 wait for CLK_PERIOD; start_i <= '0'; wait until ready_o='1';
 245                 assert output_o="01000010001000001000000000100000"
 246                 report "Error!!!"
 247                 severity failure;
 248
 249
 250                 ----------------------------------------------------------------------------------------------------------------------------------------------------
 251                 assert false
 252                 report "Success!!!.......Yahoooooooooooooo"
 253                 severity failure;
 254
 255         wait;
 256
 257     end process verify;
 258
 259 end rtl;