Kernel/armv7 - Tegra2 timer and interrupt rework
[tpg/acess2.git] / KernelLand / Kernel / arch / armv7 / platform_tegra2.h
1 /*
2  * Acess2 Kernel ARMv7 Port
3  * - By John Hodge (thePowersGang)
4  *
5  * platform_tegra2.c
6  * - Tegra2 Core code
7  */
8 #ifndef _PLATFORM__TEGRA2_H_
9 #define _PLATFORM__TEGRA2_H_
10
11 struct sTimerRegs
12 {
13         Uint32  PTV_0;  // Control / Target value
14         Uint32  PCR_0;  // Current value / IRQ clear
15 };
16 struct sTimersMap
17 {
18         struct sTimerRegs       TMR0;
19         struct sTimerRegs       TMR1;
20         // TMRUS
21         char _padding[ 0x50-0x10 ];
22
23         struct sTimerRegs       TMR2;
24         struct sTimerRegs       TMR3;
25 };
26
27 #if 0
28 struct sIRQRegs
29 {
30         Uint32  VIRQ_CPU;
31         Uint32  VIRQ_COP;
32         Uint32  VFIQ_CPU;
33         Uint32  VFIQ_COP;
34         Uint32  ISR;
35         Uint32  FIR;    // Force interrupt status
36         Uint32  FIR_SET;        // Set bit in FIR
37         Uint32  FIR_CLR;        // Clear bit in FIR
38         Uint32  CPU_IER;        // RO - Interrupt Enable register
39         Uint32  CPU_IER_SET;
40         Uint32  CPU_IER_CLR;
41         Uint32  CPU_IEP;        // 1 = FIQ
42         Uint32  COP_IER;        // RO - Interrupt Enable register
43         Uint32  COP_IER_SET;
44         Uint32  COP_IER_CLR;
45         Uint32  COP_IEP;        // 1 = FIQ
46 };
47 struct sArbGntRegs
48 {
49         Uint32  CPU_Status;
50         Uint32  CPU_Enable;
51         Uint32  COP_Status;
52         Uint32  COP_Enable;
53 };
54 struct sIRQMap
55 {
56         struct sIRQRegs Pri;
57         struct sArbGntRegs      Arb;
58         char    _pad1[0x100-sizeof(struct sIRQRegs)-sizeof(struct sIRQRegs)];
59         struct sIRQRegs Sec;
60         char    _pad2[0x100-sizeof(struct sIRQRegs)];
61         struct sIRQRegs Tri;
62         char    _pad3[0x100-sizeof(struct sIRQRegs)];
63         struct sIRQRegs Quad;
64 };
65 #endif
66
67 #endif
68

UCC git Repository :: git.ucc.asn.au