KernelLand/Modules/USB/UHCI/uhci.h

   1 /*
   2  * AcessOS Version 1
   3  * USB Stack
   4  * - Universal Host Controller Interface
   5  */
   6 #ifndef _UHCI_H_
   7 #define _UHCI_H_
   8
   9 // === TYPES ===
  10 typedef struct sUHCI_Controller tUHCI_Controller;
  11 typedef struct sUHCI_ExtraTDInfo        tUHCI_ExtraTDInfo;
  12
  13 typedef struct sUHCI_TD tUHCI_TD;
  14 typedef struct sUHCI_QH tUHCI_QH;
  15
  16 // === STRUCTURES ===
  17 struct sUHCI_ExtraTDInfo
  18 {
  19          int    Offset;
  20         tPAddr  FirstPage;
  21         tPAddr  SecondPage;
  22
  23         tUSBHostCb      Callback;
  24         void    *CallbackPtr;
  25 };
  26
  27 struct sUHCI_TD
  28 {
  29         /**
  30          * \brief Next Entry in list
  31          *
  32          * 31:4 - Address
  33          * 3 - Reserved
  34          * 2 - Depth/Breadth Select
  35          * 1 - QH/TD Select
  36          * 0 - Terminate (Last in List)
  37          */
  38         Uint32  Link;
  39
  40         /**
  41          * \brief Control and Status Field
  42          *
  43          * 31:30 - Reserved
  44          * 29 - Short Packet Detect (Input Only)
  45          * 28:27 - Number of Errors Allowed
  46          * 26 - Low Speed Device (Communicating with a low speed device)
  47          * 25 - Isynchonious Select
  48          * 24 - Interrupt on Completion (IOC)
  49          * 23:16 - Status
  50          *     23 - Active
  51          *     22 - Stalled
  52          *     21 - Data Buffer Error
  53          *     20 - Babble Detected
  54          *     19 - NAK Detected
  55          *     18 - CRC/Timout Error
  56          *     17 - Bitstuff Error
  57          *     16 - Reserved
  58          * 15:11 - Reserved
  59          * 10:0 - Actual Length (Number of bytes transfered)
  60          */
  61         Uint32  Control;
  62
  63         /**
  64          * \brief Packet Header
  65          *
  66          * 31:21 - Maximum Length (0=1, Max 0x4FF, 0x7FF=0)
  67          * 20 - Reserved
  68          * 19 - Data Toggle
  69          * 18:15 - Endpoint
  70          * 14:8 - Device Address
  71          * 7:0 - PID (Packet Identifcation) - Only 96, E1, 2D allowed
  72          *
  73          * 0x96 = Data IN
  74          * 0xE1 = Data Out
  75          * 0x2D = Setup
  76          */
  77         Uint32  Token;
  78
  79         /**
  80          * \brief Pointer to the data to send
  81          */
  82         Uint32  BufferPointer;
  83
  84         struct
  85         {
  86                 tUHCI_ExtraTDInfo       *ExtraInfo;
  87                 char    bActive;        // Allocated
  88                 Uint8   QueueIndex;     // QH, 0-127 are interrupt, 128 undef, 129 Control, 130 Bulk
  89                 char    bFreePointer;   // Free \a BufferPointer once done
  90         } _info;
  91 } __attribute__((aligned(16)));
  92
  93 struct sUHCI_QH
  94 {
  95         /**
  96          * \brief Next Entry in list
  97          *
  98          * 31:4 - Address
  99          * 3:2 - Reserved
 100          * 1 - QH/TD Select
 101          * 0 - Terminate (Last in List)
 102          */
 103         Uint32  Next;
 104
 105
 106         /**
 107          * \brief Next Entry in list
 108          *
 109          * 31:4 - Address
 110          * 3:2 - Reserved
 111          * 1 - QH/TD Select
 112          * 0 - Terminate (Last in List)
 113          */
 114         Uint32  Child;
 115
 116         /*
 117          * \note Area for software use
 118          * \brief Last TD in this list, used to add things to the end
 119          */
 120         tUHCI_TD        *_LastItem;
 121 } __attribute__((aligned(16)));
 122
 123 struct sUHCI_Controller
 124 {
 125         /**
 126          * \brief PCI Device ID
 127          */
 128         Uint16  PciId;
 129
 130         /**
 131          * \brief IO Base Address
 132          */
 133         Uint16  IOBase;
 134
 135         /**
 136          * \brief Memory Mapped-IO base address
 137          */
 138         Uint16  *MemIOMap;
 139
 140         /**
 141          * \brief IRQ Number assigned to the device
 142          */
 143          int    IRQNum;
 144
 145         /**
 146          * \brief Number of the last frame to be cleaned
 147          */
 148          int    LastCleanedFrame;
 149
 150         /**
 151          * \brief Frame list
 152          *
 153          * 31:4 - Frame Pointer
 154          * 3:2 - Reserved
 155          * 1 - QH/TD Selector
 156          * 0 - Terminate (Empty Pointer)
 157          */
 158         Uint32  *FrameList;
 159
 160         /**
 161          * \brief Physical Address of the Frame List
 162          */
 163         tPAddr  PhysFrameList;
 164
 165         tUSBHub *RootHub;
 166
 167         /**
 168          */
 169 //       int    FrameLoads[1024];
 170
 171         tPAddr          PhysTDQHPage;
 172         struct
 173         {
 174                 // 127 Interrupt Queue Heads
 175                 // - 4ms -> 256ms range of periods
 176                 tUHCI_QH        InterruptQHs[0];
 177                 tUHCI_QH        InterruptQHs_256ms[64];
 178                 tUHCI_QH        InterruptQHs_128ms[32];
 179                 tUHCI_QH        InterruptQHs_64ms [16];
 180                 tUHCI_QH        InterruptQHs_32ms [ 8];
 181                 tUHCI_QH        InterruptQHs_16ms [ 4];
 182                 tUHCI_QH        InterruptQHs_8ms  [ 2];
 183                 tUHCI_QH        InterruptQHs_4ms  [ 1];
 184                 tUHCI_QH        _padding;
 185
 186                 tUHCI_QH        ControlQH;
 187                 tUHCI_QH        BulkQH;
 188
 189                 tUHCI_TD        LocalTDPool[ (4096-(128+2)*sizeof(tUHCI_QH)) / sizeof(tUHCI_TD) ];
 190         }       *TDQHPage;
 191 };
 192
 193 // === ENUMERATIONS ===
 194 enum eUHCI_IOPorts {
 195         /**
 196          * \brief USB Command Register
 197          *
 198          * 15:8 - Reserved
 199          * 7 - Maximum Packet Size selector (1: 64 bytes, 0: 32 bytes)
 200          * 6 - Configure Flag (No Hardware Effect)
 201          * 5 - Software Debug (Don't think it will be needed)
 202          * 4 - Force Global Resume
 203          * 3 - Enter Global Suspend Mode
 204          * 2 - Global Reset (Resets all devices on the bus)
 205          * 1 - Host Controller Reset (Reset just the controller)
 206          * 0 - Run/Stop
 207          */
 208         USBCMD  = 0x00,
 209         /**
 210          * \brief USB Status Register
 211          *
 212          * 15:6 - Reserved
 213          * 5 - HC Halted, set to 1 when USBCMD:RS is set to 0
 214          * 4 - Host Controller Process Error (Errors related to the bus)
 215          * 3 - Host System Error (Errors related to the OS/PCI Bus)
 216          * 2 - Resume Detect (Set if a RESUME command is sent to the Controller)
 217          * 1 - USB Error Interrupt
 218          * 0 - USB Interrupts (Set if a transaction with the IOC bit set is completed)
 219          */
 220         USBSTS  = 0x02,
 221         /**
 222          * \brief USB Interrupt Enable Register
 223          *
 224          * 15:4 - Reserved
 225          * 3 - Short Packet Interrupt Enable
 226          * 2 - Interrupt on Complete (IOC) Enable
 227          * 1 - Resume Interrupt Enable
 228          * 0 - Timout / CRC Error Interrupt Enable
 229          */
 230         USBINTR = 0x04,
 231         /**
 232          * \brief Frame Number (Index into the Frame List)
 233          *
 234          * 15:11 - Reserved
 235          * 10:0 - Index (Incremented each approx 1ms)
 236          */
 237         FRNUM   = 0x06,
 238         /**
 239          * \brief Frame List Base Address
 240          *
 241          * 31:12 - Pysical Address >> 12
 242          * 11:0 - Reserved (Set to Zero)
 243          */
 244         FLBASEADD = 0x08,       // 32-bit
 245         /**
 246          * \brief Start-of-frame Modify Register
 247          * \note 8-bits only
 248          *
 249          * Sets the size of a frame
 250          * Frequency = (11936+n)/12000 kHz
 251          *
 252          * 7 - Reserved
 253          * 6:0 -
 254          */
 255         SOFMOD = 0x0C,  // 8bit
 256         /**
 257          * \brief Port Status and Controll Register (Port 1)
 258          *
 259          * 15:13 - Reserved
 260          * 12 - Suspend
 261          * 11:10 - Reserved
 262          * 9 - Port Reset
 263          * 8 - Low Speed Device Attached
 264          * 5:4 - Line Status
 265          * 3 - Port Enable/Disable Change - Used for detecting device removal
 266          * 2 - Port Enable/Disable
 267          * 1 - Connect Status Change
 268          * 0 - Current Connect Status
 269          */
 270         PORTSC1 = 0x10,
 271         /**
 272          * \brief Port Status and Controll Register (Port 2)
 273          *
 274          * See ::PORTSC1
 275          */
 276         PORTSC2 = 0x12
 277 };
 278
 279 #endif