7 * The communications protocol:
9 * \n used for separating packets. Caps is important.
12 * KX - keypad press where X is (ascii 0..9 or R)
13 * CXXXXX - coin balance, XXXXX is number of cents.
14 * MXYY - dispense ack/nack. X is what happened (0..MOTOR_*_FAIL), YY is the motor
15 * DX - door open/close event where X is 1 for open, 0 for closed.
18 * VXX - vend a slot XX
19 * DXXXXXXXXXXX - write the string XXXXXXXXXX to screen (10 chars)
21 * U - query current coin balance. - replies with CXXXXX
22 * GXXXXX - give change, XXXXX is the amount of the cost of the item hence change
23 * is the current value in the coin mech - XXXXX
27 #define TX_BUFFER_LEN 6 /* maximum 12 due to the way tx_int works with the FIFO */
28 extern char tx_buffer[TX_BUFFER_LEN+2]; /* \n + null terminated */
29 #define RX_BUFFER_LEN 11
30 extern volatile char rx_buffer[RX_BUFFER_LEN+1]; /* null terminated */
31 extern volatile char msg_buf[RX_BUFFER_LEN+1]; /* rx_buffer copied here w/o \n */
33 /* rx_queue_state denotes the state of rx_buffer & msg_buf. Is one of:
34 * 0: both rx_buffer & msg_buf are empty and there are no msgs
35 * 1: msg_buf has a pending msg, but rx_buffer is not yet full.
36 * 2: msg_buf has a pending msg, as does rx_buffer - further msgs will be lost
38 extern volatile u8 rx_queue_state;
40 /* tx_queue_state bits are:
41 * bit 0: if the tx_buffer has a message pending to be sent.
42 * bit 1: if the TX fifo is in use.
44 extern volatile u8 tx_queue_state;
46 extern inline void wait_for_tx_free() { while (tx_queue_state & 0x01); }
54 /*************************************/
55 /*** 16550 UART specific #defines ***/
56 /*************************************/
58 #define UART_SPEED 4915200 /* FIXME divide this by some magic number */
59 #define BAUD_RATE 9600
61 /* Register offsets for _uart_regs */
62 /* Must be accessed with DLAB low */
63 #define UART_RX_BUFFER 0x00 /* read */
64 #define UART_TX_BUFFER 0x00 /* write */
65 #define UART_INT_ENABLE 0x01
66 #define UART_INT_IDENT 0x02 /* read */
67 #define UART_FIFO_CTL 0x02 /* write */
68 #define UART_LINE_CTL 0x03
69 #define UART_MODEM_CTL 0x04
70 #define UART_LINE_STATUS 0x05
71 #define UART_MODEM_STATUS 0x06
72 #define UART_SCRATCH 0x07
74 /* Same addresses as above, but accessed with DLAB high */
75 #define UART_DLAB_LSB 0x00
76 #define UART_DLAB_MSB 0x01
78 extern volatile u8 _uart_regs[]; /* UART registers - fixed at link time */
80 /* The following #define's adapted from Minix 2.0.0's rs232.c */
82 /* Interrupt enable bits. */
83 #define IE_RECEIVER_READY 1
84 #define IE_TRANSMITTER_READY 2
85 #define IE_LINE_STATUS_CHANGE 4
86 #define IE_MODEM_STATUS_CHANGE 8
88 /* Interrupt status bits. */
89 #define IS_MODEM_STATUS_CHANGE 0x00
90 #define IS_TRANSMITTER_READY 0x02
91 #define IS_RECEIVER_READY 0x04
92 #define IS_LINE_STATUS_CHANGE 0x06
93 #define IS_FIFO_TIMEOUT 0x0C
95 /* FIFO control bits. */
96 #define FIFO_ENABLE 0x01
97 #define FIFO_RX_CLEAR 0x02
98 #define FIFO_TX_CLEAR 0x04
99 #define FIFO_DMA_ENABLE 0x08
100 #define FIFO_LVL_1 (0x00<<6)
101 #define FIFO_LVL_4 (0x01<<6)
102 #define FIFO_LVL_8 (0x10<<6)
103 #define FIFO_LVL_14 (0x11<<6)
105 /* Line control bits. */
106 #define LC_5BITS 0x00
107 #define LC_6BITS 0x01
108 #define LC_7BITS 0x10
109 #define LC_8BITS 0x11
110 #define LC_2STOP_BITS 0x04
111 #define LC_PARITY 0x08
112 #define LC_PAREVEN 0x10
113 #define LC_BREAK 0x40
116 /* Line status bits. */
117 #define LS_DATA_READY 1
118 #define LS_OVERRUN_ERR 2
119 #define LS_PARITY_ERR 4
120 #define LS_FRAMING_ERR 8
121 #define LS_BREAK_INTERRUPT 0x10
122 #define LS_TRANSMITTER_READY 0x20
124 /* Modem control bits. */
128 #endif /* _COMM_H_ */