7 * The communications protocol:
9 * \n used for separating packets. Caps is important.
12 * KX - keypad press where X is (ascii 0..9 or R)
13 * CXXXXX - coin balance, XXXXX is number of cents.
14 * MXYY - dispense ack/nack. X is what happened (0..MOTOR_*_FAIL), YY is the motor
17 * VXX - vend a slot XX
18 * DXXXXXXXXXXX - write the string XXXXXXXXXX to screen (10 chars)
20 * U - query current coin balance. - replies with CXXXXX
21 * GXXXXX - give change, XXXXX is the amount of the cost of the item hence change
22 * is the current value in the coin mech - XXXXX
26 #define TX_BUFFER_LEN 6 /* maximum 13 due to the way tx_int works with the FIFO */
27 extern char tx_buffer[TX_BUFFER_LEN+2]; /* \n + null terminated */
28 #define RX_BUFFER_LEN 11
29 extern volatile char rx_buffer[RX_BUFFER_LEN+1]; /* null terminated */
30 extern volatile char msg_buf[RX_BUFFER_LEN+1]; /* rx_buffer copied here w/o \n */
32 /* rx_queue_state denotes the state of rx_buffer & msg_buf. Is one of:
33 * 0: both rx_buffer & msg_buf are empty and there are no msgs
34 * 1: msg_buf has a pending msg, but rx_buffer is not yet full.
35 * 2: msg_buf has a pending msg, as does rx_buffer - further msgs will be lost
37 extern volatile u8 rx_queue_state;
39 /* tx_queue_state bits are:
40 * bit 0: if the tx_buffer has a message pending to be sent.
41 * bit 1: if the TX fifo is in use.
43 extern volatile u8 tx_queue_state;
48 /*************************************/
49 /*** 16550 UART specific #defines ***/
50 /*************************************/
52 #define UART_SPEED 4915200 /* FIXME divide this by some magic number */
53 #define BAUD_RATE 9600
55 /* Register offsets for _uart_regs */
56 /* Must be accessed with DLAB low */
57 #define UART_RX_BUFFER 0x00 /* read */
58 #define UART_TX_BUFFER 0x00 /* write */
59 #define UART_INT_ENABLE 0x01
60 #define UART_INT_IDENT 0x02 /* read */
61 #define UART_FIFO_CTL 0x02 /* write */
62 #define UART_LINE_CTL 0x03
63 #define UART_MODEM_CTL 0x04
64 #define UART_LINE_STATUS 0x05
65 #define UART_MODEM_STATUS 0x06
66 #define UART_SCRATCH 0x07
68 /* Same addresses as above, but accessed with DLAB high */
69 #define UART_DLAB_LSB 0x00
70 #define UART_DLAB_MSB 0x01
72 extern volatile u8 _uart_regs[]; /* UART registers - fixed at link time */
74 /* The following #define's adapted from Minix 2.0.0's rs232.c */
76 /* Interrupt enable bits. */
77 #define IE_RECEIVER_READY 1
78 #define IE_TRANSMITTER_READY 2
79 #define IE_LINE_STATUS_CHANGE 4
80 #define IE_MODEM_STATUS_CHANGE 8
82 /* Interrupt status bits. */
83 #define IS_MODEM_STATUS_CHANGE 0x00
84 #define IS_TRANSMITTER_READY 0x02
85 #define IS_RECEIVER_READY 0x04
86 #define IS_LINE_STATUS_CHANGE 0x06
87 #define IS_FIFO_TIMEOUT 0x0C
89 /* FIFO control bits. */
90 #define FIFO_ENABLE 0x01
91 #define FIFO_RX_CLEAR 0x02
92 #define FIFO_TX_CLEAR 0x04
93 #define FIFO_DMA_ENABLE 0x08
94 #define FIFO_LVL_1 (0x00<<6)
95 #define FIFO_LVL_4 (0x01<<6)
96 #define FIFO_LVL_8 (0x10<<6)
97 #define FIFO_LVL_14 (0x11<<6)
99 /* Line control bits. */
100 #define LC_5BITS 0x00
101 #define LC_6BITS 0x01
102 #define LC_7BITS 0x10
103 #define LC_8BITS 0x11
104 #define LC_2STOP_BITS 0x04
105 #define LC_PARITY 0x08
106 #define LC_PAREVEN 0x10
107 #define LC_BREAK 0x40
110 /* Line status bits. */
111 #define LS_DATA_READY 1
112 #define LS_OVERRUN_ERR 2
113 #define LS_PARITY_ERR 4
114 #define LS_FRAMING_ERR 8
115 #define LS_BREAK_INTERRUPT 0x10
116 #define LS_TRANSMITTER_READY 0x20
118 /* Modem control bits. */
122 #endif /* _COMM_H_ */