7 * The communications protocol:
9 * \n used for separating packets. Caps is important.
12 * KX - keypad press where X is (ascii 0..9 or R)
13 * CYXXXXX - coin balance, XXXXX is number of cents. Y is 0 if we have change,
15 * MXYY - dispense ack/nack. X is what happened (0..MOTOR_*_FAIL), YY is the motor
16 * DX - door open/close event where X is 1 for open, 0 for closed.
17 * PONG - response to a ping
20 * VXX - vend a slot XX
21 * DXXXXXXXXXXX - write the string XXXXXXXXXX to screen (10 chars)
23 * U - query current coin balance. - replies with CXXXXX
24 * GXXXXX - give change, XXXXX is the amount of the cost of the item hence change
25 * is the current value in the coin mech - XXXXX
26 * PING - ping. responds with PONG
30 #define TX_BUFFER_LEN 8 /* maximum 12 due to the way tx_int works with the FIFO */
31 extern char tx_buffer[TX_BUFFER_LEN+2]; /* \n + null terminated */
32 #define RX_BUFFER_LEN 11
33 extern volatile char rx_buffer[RX_BUFFER_LEN+1]; /* null terminated */
34 extern volatile char msg_buf[RX_BUFFER_LEN+1]; /* rx_buffer copied here w/o \n */
36 /* rx_queue_state denotes the state of rx_buffer & msg_buf. Is one of:
37 * 0: both rx_buffer & msg_buf are empty and there are no msgs
38 * 1: msg_buf has a pending msg, but rx_buffer is not yet full.
39 * 2: msg_buf has a pending msg, as does rx_buffer - further msgs will be lost
41 extern volatile u8 rx_queue_state;
43 /* tx_queue_state bits are:
44 * bit 0: if the tx_buffer has a message pending to be sent.
45 * bit 1: if the TX fifo is in use.
47 extern volatile u8 tx_queue_state;
49 extern inline void wait_for_tx_free() { while (tx_queue_state & 0x01); }
57 /*************************************/
58 /*** 16550 UART specific #defines ***/
59 /*************************************/
61 #define UART_SPEED 4915200 /* FIXME divide this by some magic number */
62 #define BAUD_RATE 9600
64 /* Register offsets for _uart_regs */
65 /* Must be accessed with DLAB low */
66 #define UART_RX_BUFFER 0x00 /* read */
67 #define UART_TX_BUFFER 0x00 /* write */
68 #define UART_INT_ENABLE 0x01
69 #define UART_INT_IDENT 0x02 /* read */
70 #define UART_FIFO_CTL 0x02 /* write */
71 #define UART_LINE_CTL 0x03
72 #define UART_MODEM_CTL 0x04
73 #define UART_LINE_STATUS 0x05
74 #define UART_MODEM_STATUS 0x06
75 #define UART_SCRATCH 0x07
77 /* Same addresses as above, but accessed with DLAB high */
78 #define UART_DLAB_LSB 0x00
79 #define UART_DLAB_MSB 0x01
81 extern volatile u8 _uart_regs[]; /* UART registers - fixed at link time */
83 /* The following #define's adapted from Minix 2.0.0's rs232.c */
85 /* Interrupt enable bits. */
86 #define IE_RECEIVER_READY 1
87 #define IE_TRANSMITTER_READY 2
88 #define IE_LINE_STATUS_CHANGE 4
89 #define IE_MODEM_STATUS_CHANGE 8
91 /* Interrupt status bits. */
92 #define IS_MODEM_STATUS_CHANGE 0x00
93 #define IS_TRANSMITTER_READY 0x02
94 #define IS_RECEIVER_READY 0x04
95 #define IS_LINE_STATUS_CHANGE 0x06
96 #define IS_FIFO_TIMEOUT 0x0C
98 /* FIFO control bits. */
99 #define FIFO_ENABLE 0x01
100 #define FIFO_RX_CLEAR 0x02
101 #define FIFO_TX_CLEAR 0x04
102 #define FIFO_DMA_ENABLE 0x08
103 #define FIFO_LVL_1 (0x00<<6)
104 #define FIFO_LVL_4 (0x01<<6)
105 #define FIFO_LVL_8 (0x10<<6)
106 #define FIFO_LVL_14 (0x11<<6)
108 /* Line control bits. */
109 #define LC_5BITS 0x00
110 #define LC_6BITS 0x01
111 #define LC_7BITS 0x10
112 #define LC_8BITS 0x11
113 #define LC_2STOP_BITS 0x04
114 #define LC_PARITY 0x08
115 #define LC_PAREVEN 0x10
116 #define LC_BREAK 0x40
119 /* Line status bits. */
120 #define LS_DATA_READY 1
121 #define LS_OVERRUN_ERR 2
122 #define LS_PARITY_ERR 4
123 #define LS_FRAMING_ERR 8
124 #define LS_BREAK_INTERRUPT 0x10
125 #define LS_TRANSMITTER_READY 0x20
127 /* Modem control bits. */
131 #endif /* _COMM_H_ */