2 Copyright (C) 1999 Free Software Foundation, Inc.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _M68HC11_PORTS_H
21 #define _M68HC11_PORTS_H
27 /* Flags for the definition of the 68HC11 CCR. */
28 #define M6811_S_BIT 0x80 /* Stop disable */
29 #define M6811_X_BIT 0x40 /* X-interrupt mask */
30 #define M6811_H_BIT 0x20 /* Half carry flag */
31 #define M6811_I_BIT 0x10 /* I-interrupt mask */
32 #define M6811_N_BIT 0x08 /* Negative */
33 #define M6811_Z_BIT 0x04 /* Zero */
34 #define M6811_V_BIT 0x02 /* Overflow */
35 #define M6811_C_BIT 0x01 /* Carry */
37 /* 68HC11 register address offsets (range 0..0x3F or 0..64).
38 The absolute address of the I/O register depends on the setting
39 of the M6811_INIT register. At init time, the I/O registers are
40 mapped at 0x1000. Address of registers is then:
44 #define M6811_PORTA 0x00 /* Port A register */
45 #define M6811_DDRA 0x01 /* Data direction register for port A */
46 #define M6811_PORTG 0x02 /* Port G register */
47 #define M6811_DDRG 0x03 /* Data direction register for port G */
48 #define M6811_PORTB 0x04 /* Port B register */
49 #define M6811_PORTF 0x05 /* Port F register */
50 #define M6811_PORTC 0x06 /* Port C register */
51 #define M6811_DDRC 0x07 /* Data direction register for port C */
52 #define M6811_PORTD 0x08 /* Port D register */
53 #define M6811_DDRD 0x09 /* Data direction register for port D */
54 #define M6811_PORTE 0x0A /* Port E input register */
55 #define M6811_CFORC 0x0B /* Compare Force Register */
56 #define M6811_OC1M 0x0C /* OC1 Action Mask register */
57 #define M6811_OC1D 0x0D /* OC1 Action Data register */
58 #define M6811_TCTN 0x0E /* Timer Counter Register */
59 #define M6811_TCTN_H 0x0E /* " " " High part */
60 #define M6811_TCTN_L 0x0F /* " " " Low part */
61 #define M6811_TIC1 0x10 /* Input capture 1 register */
62 #define M6811_TIC1_H 0x10 /* " " " High part */
63 #define M6811_TIC1_L 0x11 /* " " " Low part */
64 #define M6811_TIC2 0x12 /* Input capture 2 register */
65 #define M6811_TIC2_H 0x12 /* " " " High part */
66 #define M6811_TIC2_L 0x13 /* " " " Low part */
67 #define M6811_TIC3 0x14 /* Input capture 3 register */
68 #define M6811_TIC3_H 0x14 /* " " " High part */
69 #define M6811_TIC3_L 0x15 /* " " " Low part */
70 #define M6811_TOC1 0x16 /* Output Compare 1 register */
71 #define M6811_TOC1_H 0x16 /* " " " High part */
72 #define M6811_TOC1_L 0x17 /* " " " Low part */
73 #define M6811_TOC2 0x18 /* Output Compare 2 register */
74 #define M6811_TOC2_H 0x18 /* " " " High part */
75 #define M6811_TOC2_L 0x19 /* " " " Low part */
76 #define M6811_TOC3 0x1A /* Output Compare 3 register */
77 #define M6811_TOC3_H 0x1A /* " " " High part */
78 #define M6811_TOC3_L 0x1B /* " " " Low part */
79 #define M6811_TOC4 0x1C /* Output Compare 4 register */
80 #define M6811_TOC4_H 0x1C /* " " " High part */
81 #define M6811_TOC4_L 0x1D /* " " " Low part */
82 #define M6811_TOC5 0x1E /* Output Compare 5 register */
83 #define M6811_TOC5_H 0x1E /* " " " High part */
84 #define M6811_TOC5_L 0x1F /* " " " Low part */
85 #define M6811_TCTL1 0x20 /* Timer Control register 1 */
86 #define M6811_TCTL2 0x21 /* Timer Control register 2 */
87 #define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */
88 #define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */
89 #define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */
90 #define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */
91 #define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */
92 #define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */
93 #define M6811_SPCR 0x28 /* SPI Control register */
94 #define M6811_SPSR 0x29 /* SPI Status register */
95 #define M6811_SPDR 0x2A /* SPI Data register */
96 #define M6811_BAUD 0x2B /* SCI Baud register */
97 #define M6811_SCCR1 0x2C /* SCI Control register 1 */
98 #define M6811_SCCR2 0x2D /* SCI Control register 2 */
99 #define M6811_SCSR 0x2E /* SCI Status register */
100 #define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */
101 #define M6811_ADCTL 0x30 /* A/D Control register */
102 #define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */
103 #define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */
104 #define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */
105 #define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */
106 #define M6811__RES35 0x35
107 #define M6811__RES36 0x36
108 #define M6811__RES37 0x37
109 #define M6811__RES38 0x38
110 #define M6811_OPTION 0x39 /* System Configuration Options */
111 #define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */
112 #define M6811_PPROG 0x3B /* EEPROM Programming Control Register */
113 #define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */
114 #define M6811_INIT 0x3D /* Ram and I/O mapping register */
115 #define M6811_TEST1 0x3E /* Factory test control register */
116 #define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */
118 /* Flags of the CONFIG register (in EEPROM). */
119 #define M6811_NOSEC 0x08 /* Security mode disable */
120 #define M6811_NOCOP 0x04 /* COP system disable */
121 #define M6811_ROMON 0x02 /* Enable on-chip rom */
122 #define M6811_EEON 0x01 /* Enable on-chip eeprom */
124 /* Flags of the PPROG register. */
125 #define M6811_BYTE 0x10 /* Byte mode */
126 #define M6811_ROW 0x08 /* Row mode */
127 #define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */
128 #define M6811_EELAT 0x02 /* EEPROM Latch Control */
129 #define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */
131 /* Flags of the PIOC register. */
132 #define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */
133 #define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */
134 #define M6811_CWOM 0x20 /* Port C Wire OR mode */
135 #define M6811_HNDS 0x10 /* Handshake mode */
136 #define M6811_OIN 0x08 /* Output or Input handshaking */
137 #define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */
138 #define M6811_EGA 0x02 /* Active Edge for Strobe A */
139 #define M6811_INVB 0x01 /* Invert Strobe B */
141 /* Flags of the SCCR1 register. */
142 #define M6811_R8 0x80 /* Receive Data bit 8 */
143 #define M6811_T8 0x40 /* Transmit data bit 8 */
144 #define M6811__SCCR1_5 0x20 /* Unused */
145 #define M6811_M 0x10 /* SCI Character length */
146 #define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */
148 /* Flags of the SCCR2 register. */
149 #define M6811_TIE 0x80 /* Transmit Interrupt enable */
150 #define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */
151 #define M6811_RIE 0x20 /* Receive Interrupt Enable */
152 #define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */
153 #define M6811_TE 0x08 /* Transmit Enable */
154 #define M6811_RE 0x04 /* Receive Enable */
155 #define M6811_RWU 0x02 /* Receiver Wake Up */
156 #define M6811_SBK 0x01 /* Send Break */
158 /* Flags of the SCSR register. */
159 #define M6811_TDRE 0x80 /* Transmit Data Register Empty */
160 #define M6811_TC 0x40 /* Transmit Complete */
161 #define M6811_RDRF 0x20 /* Receive Data Register Full */
162 #define M6811_IDLE 0x10 /* Idle Line Detect */
163 #define M6811_OR 0x08 /* Overrun Error */
164 #define M6811_NF 0x04 /* Noise Flag */
165 #define M6811_FE 0x02 /* Framing Error */
166 #define M6811__SCSR_0 0x01 /* Unused */
168 /* Flags of the BAUD register. */
169 #define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */
170 #define M6811__BAUD_6 0x40 /* Not used */
171 #define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */
172 #define M6811_SCP0 0x10
173 #define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */
174 #define M6811_SCR2 0x04 /* SCI Baud rate select */
175 #define M6811_SCR1 0x02
176 #define M6811_SCR0 0x01
178 #define M6811_BAUD_DIV_1 (0)
179 #define M6811_BAUD_DIV_3 (M6811_SCP0)
180 #define M6811_BAUD_DIV_4 (M6811_SCP1)
181 #define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0)
183 /* Flags of the SPCR register. */
184 #define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */
185 #define M6811_SPE 0x40 /* Serial Peripheral System Enable */
186 #define M6811_DWOM 0x20 /* Port D Wire-OR mode option */
187 #define M6811_MSTR 0x10 /* Master Mode Select */
188 #define M6811_CPOL 0x08 /* Clock Polarity */
189 #define M6811_CPHA 0x04 /* Clock Phase */
190 #define M6811_SPR1 0x02 /* SPI Clock Rate Select */
191 #define M6811_SPR0 0x01
193 /* Flags of the SPSR register. */
194 #define M6811_SPIF 0x80 /* SPI Transfer Complete flag */
195 #define M6811_WCOL 0x40 /* Write Collision */
196 #define M6811_MODF 0x10 /* Mode Fault */
198 /* Flags of the ADCTL register. */
199 #define M6811_CCF 0x80 /* Conversions Complete Flag */
200 #define M6811_SCAN 0x20 /* Continuous Scan Control */
201 #define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */
202 #define M6811_CD 0x08 /* Channel Select D */
203 #define M6811_CC 0x04 /* C */
204 #define M6811_CB 0x02 /* B */
205 #define M6811_CA 0x01 /* A */
207 /* Flags of the CFORC register. */
208 #define M6811_FOC1 0x80 /* Force Output Compare 1 */
209 #define M6811_FOC2 0x40 /* 2 */
210 #define M6811_FOC3 0x20 /* 3 */
211 #define M6811_FOC4 0x10 /* 4 */
212 #define M6811_FOC5 0x08 /* 5 */
214 /* Flags of the OC1M register. */
215 #define M6811_OC1M7 0x80 /* Output Compare 7 */
216 #define M6811_OC1M6 0x40 /* 6 */
217 #define M6811_OC1M5 0x20 /* 5 */
218 #define M6811_OC1M4 0x10 /* 4 */
219 #define M6811_OC1M3 0x08 /* 3 */
221 /* Flags of the OC1D register. */
222 #define M6811_OC1D7 0x80
223 #define M6811_OC1D6 0x40
224 #define M6811_OC1D5 0x20
225 #define M6811_OC1D4 0x10
226 #define M6811_OC1D3 0x08
228 /* Flags of the TCTL1 register. */
229 #define M6811_OM2 0x80 /* Output Mode 2 */
230 #define M6811_OL2 0x40 /* Output Level 2 */
231 #define M6811_OM3 0x20
232 #define M6811_OL3 0x10
233 #define M6811_OM4 0x08
234 #define M6811_OL4 0x04
235 #define M6811_OM5 0x02
236 #define M6811_OL5 0x01
238 /* Flags of the TCTL2 register. */
239 #define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */
240 #define M6811_EDG1A 0x10
241 #define M6811_EDG2B 0x08 /* Input 2 */
242 #define M6811_EDG2A 0x04
243 #define M6811_EDG3B 0x02 /* Input 3 */
244 #define M6811_EDG3A 0x01
246 /* Flags of the TMSK1 register. */
247 #define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */
248 #define M6811_OC2I 0x40 /* 2 */
249 #define M6811_OC3I 0x20 /* 3 */
250 #define M6811_OC4I 0x10 /* 4 */
251 #define M6811_OC5I 0x08 /* 5 */
252 #define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */
253 #define M6811_IC2I 0x02 /* 2 */
254 #define M6811_IC3I 0x01 /* 3 */
256 /* Flags of the TFLG1 register. */
257 #define M6811_OC1F 0x80 /* Output Compare 1 Flag */
258 #define M6811_OC2F 0x40 /* 2 */
259 #define M6811_OC3F 0x20 /* 3 */
260 #define M6811_OC4F 0x10 /* 4 */
261 #define M6811_OC5F 0x08 /* 5 */
262 #define M6811_IC1F 0x04 /* Input Capture 1 Flag */
263 #define M6811_IC2F 0x02 /* 2 */
264 #define M6811_IC3F 0x01 /* 3 */
266 /* Flags of Timer Interrupt Mask Register 2 (TMSK2). */
267 #define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */
268 #define M6811_RTII 0x40 /* RTI Interrupt Enable */
269 #define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */
270 #define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */
271 #define M6811_PR1 0x02 /* Timer prescaler */
272 #define M6811_PR0 0x01 /* Timer prescaler */
273 #define M6811_TPR_1 0x00 /* " " prescale div 1 */
274 #define M6811_TPR_4 0x01 /* " " prescale div 4 */
275 #define M6811_TPR_8 0x02 /* " " prescale div 8 */
276 #define M6811_TPR_16 0x03 /* " " prescale div 16 */
278 /* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */
279 #define M6811_TOF 0x80 /* Timer overflow bit */
280 #define M6811_RTIF 0x40 /* Read time interrupt flag */
281 #define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */
282 #define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */
284 /* Flags of Pulse Accumulator Control Register (PACTL). */
285 #define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */
286 #define M6811_PAEN 0x40 /* Pulse accumulator system enable */
287 #define M6811_PAMOD 0x20 /* Pulse accumulator mode */
288 #define M6811_PEDGE 0x10 /* Pulse accumulator edge control */
289 #define M6811_RTR1 0x02 /* RTI Interrupt rates select */
290 #define M6811_RTR0 0x01 /* " " " " */
292 /* Flags of the Options register. */
293 #define M6811_ADPU 0x80 /* A/D Powerup */
294 #define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */
295 #define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */
296 #define M6811_DLY 0x10 /* Stop exit turn on delay */
297 #define M6811_CME 0x08 /* Clock Monitor enable */
298 #define M6811_CR1 0x02 /* COP timer rate select */
299 #define M6811_CR0 0x01 /* COP timer rate select */
301 /* Flags of the HPRIO register. */
302 #define M6811_RBOOT 0x80 /* Read Bootstrap ROM */
303 #define M6811_SMOD 0x40 /* Special Mode */
304 #define M6811_MDA 0x20 /* Mode Select A */
305 #define M6811_IRV 0x10 /* Internal Read Visibility */
306 #define M6811_PSEL3 0x08 /* Priority Select */
307 #define M6811_PSEL2 0x04
308 #define M6811_PSEL1 0x02
309 #define M6811_PSEL0 0x01
311 #define M6811_IO_SIZE (0x40)
313 /* The I/O registers are represented by a volatile array.
314 Address if fixed at link time. */
315 extern volatile unsigned char _io_ports[];
318 extern unsigned short get_timer_counter (void);
319 extern void set_timer_counter (unsigned short);
320 extern unsigned short get_input_capture_1 (void);
321 extern void set_input_capture_1 (unsigned short);
322 extern unsigned short get_input_capture_2 (void);
323 extern void set_input_capture_2 (unsigned short);
324 extern unsigned short get_input_capture_3 (void);
325 extern void set_input_capture_3 (unsigned short);
326 extern unsigned short get_output_compare_1 (void);
327 extern void set_output_compare_1 (unsigned short);
328 extern unsigned short get_output_compare_2 (void);
329 extern void set_output_compare_2 (unsigned short);
330 extern unsigned short get_output_compare_3 (void);
331 extern void set_output_compare_3 (unsigned short);
332 extern unsigned short get_output_compare_4 (void);
333 extern void set_output_compare_4 (unsigned short);
334 extern unsigned short get_output_compare_5 (void);
335 extern void set_output_compare_5 (unsigned short);
336 extern void set_bus_expanded (void);
337 extern void set_bus_single_chip (void);
338 extern void cop_reset (void);
339 extern void cop_optional_reset (void);
340 extern void timer_acknowledge (void);
341 extern void timer_initialize_rate (unsigned char);
344 extern inline unsigned short
345 get_timer_counter (void)
347 return ((unsigned volatile short*) &_io_ports[M6811_TCTN_H])[0];
351 set_timer_counter (unsigned short value)
353 ((unsigned volatile short*) &_io_ports[M6811_TCTN_H])[0] = value;
356 extern inline unsigned short
357 get_input_capture_1 (void)
359 return ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0];
363 set_input_capture_1 (unsigned short value)
365 ((unsigned volatile short*) &_io_ports[M6811_TIC1_H])[0] = value;
368 extern inline unsigned short
369 get_input_capture_2 (void)
371 return ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0];
375 set_input_capture_2 (unsigned short value)
377 ((unsigned volatile short*) &_io_ports[M6811_TIC2_H])[0] = value;
380 extern inline unsigned short
381 get_input_capture_3 (void)
383 return ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0];
387 set_input_capture_3 (unsigned short value)
389 ((unsigned volatile short*) &_io_ports[M6811_TIC3_H])[0] = value;
392 /* Get output compare 16-bit register. */
393 extern inline unsigned short
394 get_output_compare_1 (void)
396 return ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0];
400 set_output_compare_1 (unsigned short value)
402 ((unsigned volatile short*) &_io_ports[M6811_TOC1_H])[0] = value;
405 extern inline unsigned short
406 get_output_compare_2 (void)
408 return ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0];
412 set_output_compare_2 (unsigned short value)
414 ((unsigned volatile short*) &_io_ports[M6811_TOC2_H])[0] = value;
417 extern inline unsigned short
418 get_output_compare_3 (void)
420 return ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0];
424 set_output_compare_3 (unsigned short value)
426 ((unsigned volatile short*) &_io_ports[M6811_TOC3_H])[0] = value;
429 extern inline unsigned short
430 get_output_compare_4 (void)
432 return ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0];
436 set_output_compare_4 (unsigned short value)
438 ((unsigned volatile short*) &_io_ports[M6811_TOC4_H])[0] = value;
441 extern inline unsigned short
442 get_output_compare_5 (void)
444 return ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0];
448 set_output_compare_5 (unsigned short value)
450 ((unsigned volatile short*) &_io_ports[M6811_TOC5_H])[0] = value;
454 /* Set the board in the expanded mode to get access to external bus. */
456 set_bus_expanded (void)
458 _io_ports[M6811_HPRIO] |= M6811_MDA;
462 /* Set the board in single chip mode. */
464 set_bus_single_chip (void)
466 _io_ports[M6811_HPRIO] &= ~M6811_MDA;
473 _io_ports[M6811_COPRST] = 0x55;
474 _io_ports[M6811_COPRST] = 0xAA;
478 cop_optional_reset (void)
480 #if defined(M6811_USE_COP) && M6811_USE_COP == 1
485 /* Acknowledge the timer interrupt. */
487 timer_acknowledge (void)
489 _io_ports[M6811_TFLG2] = M6811_RTIF;
492 /* Initialize the timer. */
494 timer_initialize_rate (unsigned char divisor)
496 _io_ports[M6811_TMSK2] = M6811_RTII | divisor;
504 #endif /* _M68HC11_PORTS_H */