};\r
Uint16 oc;\r
};\r
- Uint16 revision;\r
+ Uint8 revision, progif;\r
Uint32 ConfigCache[256/4];\r
char Name[8];\r
tVFS_Node Node;\r
int PCI_Install(char **Arguments);\r
int PCI_ScanBus(int ID, int bFill);\r
\r
-char *PCI_ReadDirRoot(tVFS_Node *node, int pos);\r
-tVFS_Node *PCI_FindDirRoot(tVFS_Node *node, const char *filename);\r
-Uint64 PCI_ReadDevice(tVFS_Node *node, Uint64 pos, Uint64 length, void *buffer);\r
-\r
-#if 0\r
- int PCI_CountDevices(Uint16 vendor, Uint16 device, Uint16 fcn);\r
- int PCI_GetDevice(Uint16 vendor, Uint16 device, Uint16 fcn, int idx);\r
- int PCI_GetDeviceByClass(Uint16 class, Uint16 mask, int prev);\r
-Uint8 PCI_GetIRQ(int id);\r
-Uint32 PCI_GetBAR0(int id);\r
-Uint32 PCI_GetBAR1(int id);\r
-Uint32 PCI_GetBAR2(int id);\r
-Uint32 PCI_GetBAR3(int id);\r
-Uint32 PCI_GetBAR4(int id);\r
-Uint32 PCI_GetBAR5(int id);\r
-Uint16 PCI_AssignPort(int id, int bar, int count);\r
-#endif\r
-\r
- int PCI_EnumDevice(Uint16 bus, Uint16 dev, Uint16 fcn, tPCIDevice *info);\r
+char *PCI_int_ReadDirRoot(tVFS_Node *node, int pos);\r
+tVFS_Node *PCI_int_FindDirRoot(tVFS_Node *node, const char *filename);\r
+Uint64 PCI_int_ReadDevice(tVFS_Node *node, Uint64 pos, Uint64 length, void *buffer);\r
+ int PCI_int_EnumDevice(Uint16 bus, Uint16 dev, Uint16 fcn, tPCIDevice *info);\r
\r
// === GLOBALS ===\r
MODULE_DEFINE(0, 0x0100, PCI, PCI_Install, NULL, NULL);\r
.Size = -1,\r
.NumACLs = 1,\r
.ACLs = &gVFS_ACL_EveryoneRX,\r
- .ReadDir = PCI_ReadDirRoot,\r
- .FindDir = PCI_FindDirRoot\r
+ .ReadDir = PCI_int_ReadDirRoot,\r
+ .FindDir = PCI_int_FindDirRoot\r
}\r
};\r
Uint32 *gaPCI_PortBitmap = NULL;\r
for( fcn = 0; fcn < 8; fcn++ ) // Max 8 functions per device\r
{\r
// Check if the device/function exists\r
- if(!PCI_EnumDevice(BusID, dev, fcn, &devInfo))\r
+ if(!PCI_int_EnumDevice(BusID, dev, fcn, &devInfo))\r
continue;\r
\r
if(devInfo.oc == PCI_OC_PCIBRIDGE)\r
}\r
\r
/**\r
- * \fn char *PCI_ReadDirRoot(tVFS_Node *Node, int Pos)\r
* \brief Read from Root of PCI Driver\r
*/\r
-char *PCI_ReadDirRoot(tVFS_Node *Node, int Pos)\r
+char *PCI_int_ReadDirRoot(tVFS_Node *Node, int Pos)\r
{\r
ENTER("pNode iPos", Node, Pos);\r
if(Pos < 0 || Pos >= giPCI_DeviceCount) {\r
return strdup( gPCI_Devices[Pos].Name );\r
}\r
/**\r
- * \fn tVFS_Node *PCI_FindDirRoot(tVFS_Node *node, const char *filename)\r
*/\r
-tVFS_Node *PCI_FindDirRoot(tVFS_Node *node, const char *filename)\r
+tVFS_Node *PCI_int_FindDirRoot(tVFS_Node *node, const char *filename)\r
{\r
int bus,slot,fcn;\r
int i;\r
}\r
\r
/**\r
- * \fn Uint64 PCI_ReadDevice(tVFS_Node *node, Uint64 pos, Uint64 length, void *buffer)\r
*/\r
-Uint64 PCI_ReadDevice(tVFS_Node *node, Uint64 pos, Uint64 length, void *buffer)\r
+Uint64 PCI_int_ReadDevice(tVFS_Node *node, Uint64 pos, Uint64 length, void *buffer)\r
{ \r
if( pos + length > 256 ) return 0;\r
\r
\r
// --- Kernel Code Interface ---\r
/**\r
- \fn int PCI_CountDevices(Uint16 vendor, Uint16 device, Uint16 fcn)\r
- \brief Counts the devices with the specified codes\r
- \param vendor Vendor ID\r
- \param device Device ID\r
- \param fcn Function ID\r
-*/\r
-int PCI_CountDevices(Uint16 vendor, Uint16 device, Uint16 fcn)\r
+ * \brief Counts the devices with the specified codes\r
+ * \param vendor Vendor ID\r
+ * \param device Device ID\r
+ */\r
+int PCI_CountDevices(Uint16 vendor, Uint16 device)\r
{\r
int i, ret=0;\r
for(i=0;i<giPCI_DeviceCount;i++)\r
{\r
if(gPCI_Devices[i].vendor != vendor) continue;\r
if(gPCI_Devices[i].device != device) continue;\r
- if(gPCI_Devices[i].fcn != fcn) continue;\r
ret ++;\r
}\r
return ret;\r
}\r
\r
/**\r
- \fn int PCI_GetDevice(Uint16 vendor, Uint16 device, Uint16 fcn, int idx)\r
- \brief Gets the ID of the specified PCI device\r
- \param vendor Vendor ID\r
- \param device Device ID\r
- \param fcn Function IDs\r
- \param idx Number of matching entry wanted\r
-*/\r
-int PCI_GetDevice(Uint16 vendor, Uint16 device, Uint16 fcn, int idx)\r
+ * \brief Gets the ID of the specified PCI device\r
+ * \param vendor Vendor ID\r
+ * \param device Device ID\r
+ * \param idx Number of matching entry wanted\r
+ */\r
+tPCIDev PCI_GetDevice(Uint16 vendor, Uint16 device, int idx)\r
{\r
int i, j=0;\r
for(i=0;i<giPCI_DeviceCount;i++)\r
{\r
if(gPCI_Devices[i].vendor != vendor) continue;\r
if(gPCI_Devices[i].device != device) continue;\r
- if(gPCI_Devices[i].fcn != fcn) continue;\r
if(j == idx) return i;\r
j ++;\r
}\r
}\r
\r
/**\r
- * \fn int PCI_GetDeviceByClass(Uint16 class, Uint16 mask, int prev)\r
* \brief Gets the ID of a device by it's class code\r
* \param class Class Code\r
* \param mask Mask for class comparison\r
* \param prev ID of previous device (-1 for no previous)\r
*/\r
-int PCI_GetDeviceByClass(Uint16 class, Uint16 mask, int prev)\r
+tPCIDev PCI_GetDeviceByClass(Uint16 class, Uint16 mask, tPCIDev prev)\r
{\r
int i;\r
// Check if prev is negative (meaning get first)\r
return -1;\r
}\r
\r
-/**\r
- \fn Uint8 PCI_GetIRQ(int id)\r
-*/\r
-Uint8 PCI_GetIRQ(int id)\r
+int PCI_GetDeviceInfo(tPCIDev ID, Uint16 *Vendor, Uint16 *Device, Uint16 *Class)\r
{\r
- if(id < 0 || id >= giPCI_DeviceCount)\r
- return 0;\r
- return gPCI_Devices[id].ConfigCache[15];\r
- //return PCI_CfgReadByte( gPCI_Devices[id].bus, gPCI_Devices[id].slot, gPCI_Devices[id].fcn, 0x3C);\r
+ tPCIDevice *dev = &gPCI_Devices[ID];\r
+ if(ID < 0 || ID >= giPCI_DeviceCount) return 1;\r
+ \r
+ if(Vendor) *Vendor = dev->vendor;\r
+ if(Device) *Device = dev->device;\r
+ if(Class) *Class = dev->oc;\r
+ return 0;\r
}\r
\r
-/**\r
- \fn Uint32 PCI_GetBAR0(int id)\r
-*/\r
-Uint32 PCI_GetBAR0(int id)\r
+int PCI_GetDeviceVersion(tPCIDev ID, Uint8 *Revision, Uint8 *ProgIF)\r
{\r
- if(id < 0 || id >= giPCI_DeviceCount)\r
- return 0;\r
- return gPCI_Devices[id].ConfigCache[4];\r
+ tPCIDevice *dev = &gPCI_Devices[ID];\r
+ if(ID < 0 || ID >= giPCI_DeviceCount) return 1;\r
+ \r
+ if(Revision) *Revision = dev->revision;\r
+ if(ProgIF) *ProgIF = dev->progif;\r
+ return 0;\r
}\r
\r
-/**\r
- \fn Uint32 PCI_GetBAR1(int id)\r
-*/\r
-Uint32 PCI_GetBAR1(int id)\r
+int PCI_GetDeviceSubsys(tPCIDev ID, Uint16 *SubsystemVendor, Uint16 *SubsystemID)\r
{\r
- if(id < 0 || id >= giPCI_DeviceCount)\r
- return 0;\r
- return gPCI_Devices[id].ConfigCache[5];\r
+ tPCIDevice *dev = &gPCI_Devices[ID];\r
+ if(ID < 0 || ID >= giPCI_DeviceCount) return 1;\r
+ \r
+ if(SubsystemVendor) *SubsystemVendor = dev->ConfigCache[0x2c/4] & 0xFFFF;\r
+ if(SubsystemID) *SubsystemID = dev->ConfigCache[0x2c/4] >> 16;\r
+\r
+ return 0;\r
}\r
\r
-/**\r
- \fn Uint32 PCI_GetBAR2(int id)\r
-*/\r
-Uint32 PCI_GetBAR2(int id)\r
+Uint32 PCI_ConfigRead(tPCIDev ID, int Offset, int Size)\r
{\r
- if(id < 0 || id >= giPCI_DeviceCount)\r
+ tPCIDevice *dev;\r
+ Uint32 dword;\r
+ if( ID < 0 || ID >= giPCI_DeviceCount ) return 0;\r
+ if( Offset < 0 || Offset > 256 ) return 0;\r
+\r
+ // TODO: Should I support non-aligned reads?\r
+ if( Offset & (Size - 1) ) return 0;\r
+\r
+ dev = &gPCI_Devices[ID];\r
+\r
+ dword = PCI_CfgReadDWord(dev->bus, dev->slot, dev->fcn, Offset / 4);\r
+ gPCI_Devices[ID].ConfigCache[Offset/4] = dword;\r
+ switch( Size )\r
+ {\r
+ case 1: return (dword >> (8 * (Offset&3))) & 0xFF;\r
+ case 2: return (dword >> (8 * (Offset&2))) & 0xFFFF;\r
+ case 4: return dword;\r
+ default:\r
return 0;\r
- return gPCI_Devices[id].ConfigCache[6];\r
+ }\r
}\r
\r
-/**\r
- \fn Uint32 PCI_GetBAR3(int id)\r
-*/\r
-Uint32 PCI_GetBAR3(int id)\r
+void PCI_ConfigWrite(tPCIDev ID, int Offset, int Size, Uint32 Value)\r
{\r
- if(id < 0 || id >= giPCI_DeviceCount)\r
- return 0;\r
- return gPCI_Devices[id].ConfigCache[7];\r
+ tPCIDevice *dev;\r
+ Uint32 dword;\r
+ int shift;\r
+ if( ID < 0 || ID >= giPCI_DeviceCount ) return ;\r
+ if( Offset < 0 || Offset > 256 ) return ;\r
+ \r
+ dev = &gPCI_Devices[ID];\r
+\r
+ dword = PCI_CfgReadDWord(dev->bus, dev->slot, dev->fcn, Offset/4);\r
+ switch(Size)\r
+ {\r
+ case 1:\r
+ shift = (Offset&3)*8;\r
+ dword &= ~(0xFF << shift);\r
+ dword |= Value << shift;\r
+ break;\r
+ case 2:\r
+ shift = (Offset&2)*8;\r
+ dword &= ~(0xFFFF << shift);\r
+ dword |= Value << shift;\r
+ break;\r
+ case 4:\r
+ dword = Value;\r
+ break;\r
+ default:\r
+ return;\r
+ }\r
+ PCI_CfgWriteDWord(dev->bus, dev->slot, dev->fcn, Offset/4, dword);\r
}\r
\r
/**\r
- \fn Uint32 PCI_GetBAR4(int id)\r
-*/\r
-Uint32 PCI_GetBAR4(int id)\r
+ * \brief Get the IRQ assigned to a device\r
+ */\r
+Uint8 PCI_GetIRQ(tPCIDev id)\r
{\r
if(id < 0 || id >= giPCI_DeviceCount)\r
return 0;\r
- return gPCI_Devices[id].ConfigCache[8];\r
+ return gPCI_Devices[id].ConfigCache[15] & 0xFF;\r
+ //return PCI_CfgReadByte( gPCI_Devices[id].bus, gPCI_Devices[id].slot, gPCI_Devices[id].fcn, 0x3C);\r
}\r
\r
/**\r
- \fn Uint32 PCI_GetBAR5(int id)\r
-*/\r
-Uint32 PCI_GetBAR5(int id)\r
+ * \brief Read the a BAR (base address register) from the PCI config space\r
+ */\r
+Uint32 PCI_GetBAR(tPCIDev id, int BARNum)\r
{\r
if(id < 0 || id >= giPCI_DeviceCount)\r
return 0;\r
- return gPCI_Devices[id].ConfigCache[9];\r
+ if(BARNum < 0 || BARNum >= 6)\r
+ return 0;\r
+ return gPCI_Devices[id].ConfigCache[4+BARNum];\r
}\r
\r
-Uint16 PCI_AssignPort(int id, int bar, int count)\r
+#if 0\r
+/**\r
+ * \brief Assign a port to a BAR\r
+ */\r
+Uint16 PCI_AssignPort(tPCIDev ID, int bar, int Count)\r
{\r
#if 1\r
Uint16 rv;\r
tPCIDevice *dev;\r
\r
if(id < 0 || id >= giPCI_DeviceCount) return 0;\r
- if(bar < 0 || bar > 5) return 0;\r
+ if(bar < 0 || bar >= 6) return 0;\r
dev = &gPCI_Devices[id];\r
\r
rv = PCI_CfgReadDWord( dev->bus, dev->slot, dev->fcn, 0x10+bar*4 );\r
return portVals;\r
#endif\r
}\r
+#endif\r
\r
/**\r
- * \fn int PCI_EnumDevice(Uint16 bus, Uint16 slot, Uint16 fcn, tPCIDevice *info)\r
* \brief Get device information for a slot/function\r
*/\r
-int PCI_EnumDevice(Uint16 bus, Uint16 slot, Uint16 fcn, tPCIDevice *info)\r
+int PCI_int_EnumDevice(Uint16 bus, Uint16 slot, Uint16 fcn, tPCIDevice *info)\r
{\r
Uint16 vendor;\r
int i;\r
info->Node.NumACLs = 1;\r
info->Node.ACLs = &gVFS_ACL_EveryoneRO;\r
\r
- info->Node.Read = PCI_ReadDevice;\r
+ info->Node.Read = PCI_int_ReadDevice;\r
\r
return 1;\r
}\r
EXPORT(PCI_CountDevices);\r
EXPORT(PCI_GetDevice);\r
EXPORT(PCI_GetDeviceByClass);\r
-EXPORT(PCI_AssignPort);\r
+EXPORT(PCI_GetDeviceInfo);\r
+EXPORT(PCI_GetDeviceVersion);\r
+EXPORT(PCI_GetDeviceSubsys);\r
+//EXPORT(PCI_AssignPort);\r
+EXPORT(PCI_GetBAR);\r
EXPORT(PCI_GetIRQ);\r
//*/\r
-/*\r
- * Acess 2 USB Stack\r
- * Universal Host Controller Interface\r
- */\r
-#define DEBUG 1\r
-#include <acess.h>\r
-#include <vfs.h>\r
-#include <drv_pci.h>\r
-#include "usb.h"\r
-#include "uhci.h"\r
-\r
-// === CONSTANTS ===\r
-#define MAX_CONTROLLERS 4\r
-#define NUM_TDs 1024\r
-\r
-// === PROTOTYPES ===\r
- int UHCI_Initialise();\r
-void UHCI_Cleanup();\r
- int UHCI_IOCtl(tVFS_Node *node, int id, void *data);\r
- int UHCI_Int_InitHost(tUHCI_Controller *Host);\r
-\r
+/*
+ * Acess 2 USB Stack
+ * Universal Host Controller Interface
+ */
+#define DEBUG 1
+#include <acess.h>
+#include <vfs.h>
+#include <drv_pci.h>
+#include "usb.h"
+#include "uhci.h"
+
+// === CONSTANTS ===
+#define MAX_CONTROLLERS 4
+#define NUM_TDs 1024
+
+// === PROTOTYPES ===
+ int UHCI_Initialise();
+void UHCI_Cleanup();
+ int UHCI_IOCtl(tVFS_Node *node, int id, void *data);
+ int UHCI_Int_InitHost(tUHCI_Controller *Host);
+
// === GLOBALS ===
-//Uint gaFrameList[1024];\r
-tUHCI_TD gaUHCI_TDPool[NUM_TDs];\r
-tUHCI_Controller gUHCI_Controllers[MAX_CONTROLLERS];\r
-\r
-// === CODE ===\r
-/**\r
- * \fn int UHCI_Initialise()\r
- * \brief Called to initialise the UHCI Driver\r
- */\r
-int UHCI_Initialise()\r
-{\r
- int i=0, id=-1;\r
- int ret;\r
- \r
- ENTER("");\r
- \r
- // Enumerate PCI Bus, getting a maximum of `MAX_CONTROLLERS` devices\r
- while( (id = PCI_GetDeviceByClass(0x0C03, 0xFFFF, id)) >= 0 && i < MAX_CONTROLLERS )\r
- {\r
- // NOTE: Check "protocol" from PCI?\r
- \r
- gUHCI_Controllers[i].PciId = id;\r
- // Assign a port range (BAR4, Reserve 32 ports)\r
- //base = PCI_AssignPort( id, 4, 0x20 );\r
- gUHCI_Controllers[i].IOBase = PCI_GetBAR4(id);\r
- gUHCI_Controllers[i].IRQNum = PCI_GetIRQ(id);\r
- \r
- Log("[USB ] Controller PCI #%i: IO Base = 0x%x, IRQ %i",\r
- id, gUHCI_Controllers[i].IOBase, gUHCI_Controllers[i].IRQNum);\r
- \r
- // Initialise Host\r
- ret = UHCI_Int_InitHost(&gUHCI_Controllers[i]);\r
- // Detect an error\r
- if(ret != 0) {\r
- LEAVE('i', ret);\r
- return ret;\r
- }\r
- \r
- i ++;\r
- }\r
- if(i == MAX_CONTROLLERS) {\r
- Warning("[UHCI ] Over "EXPAND_STR(MAX_CONTROLLERS)" UHCI controllers detected, ignoring rest");\r
- }\r
- LEAVE('i', i);\r
- return i;\r
-}\r
-\r
-/**\r
- * \fn void UHCI_Cleanup()\r
- * \brief Called just before module is unloaded\r
- */\r
-void UHCI_Cleanup()\r
-{\r
+//Uint gaFrameList[1024];
+tUHCI_TD gaUHCI_TDPool[NUM_TDs];
+tUHCI_Controller gUHCI_Controllers[MAX_CONTROLLERS];
+
+// === CODE ===
+/**
+ * \fn int UHCI_Initialise()
+ * \brief Called to initialise the UHCI Driver
+ */
+int UHCI_Initialise()
+{
+ int i=0, id=-1;
+ int ret;
+
+ ENTER("");
+
+ // Enumerate PCI Bus, getting a maximum of `MAX_CONTROLLERS` devices
+ while( (id = PCI_GetDeviceByClass(0x0C03, 0xFFFF, id)) >= 0 && i < MAX_CONTROLLERS )
+ {
+ // NOTE: Check "protocol" from PCI?
+
+ gUHCI_Controllers[i].PciId = id;
+ // Assign a port range (BAR4, Reserve 32 ports)
+ gUHCI_Controllers[i].IOBase = PCI_GetBAR(id, 4);
+ gUHCI_Controllers[i].IRQNum = PCI_GetIRQ(id);
+
+ Log("[USB ] Controller PCI #%i: IO Base = 0x%x, IRQ %i",
+ id, gUHCI_Controllers[i].IOBase, gUHCI_Controllers[i].IRQNum);
+
+ // Initialise Host
+ ret = UHCI_Int_InitHost(&gUHCI_Controllers[i]);
+ // Detect an error
+ if(ret != 0) {
+ LEAVE('i', ret);
+ return ret;
+ }
+
+ i ++;
+ }
+ if(i == MAX_CONTROLLERS) {
+ Log_Warning("UHCI", "Over "EXPAND_STR(MAX_CONTROLLERS)" UHCI controllers detected, ignoring rest");
+ }
+ LEAVE('i', i);
+ return i;
+}
+
+/**
+ * \fn void UHCI_Cleanup()
+ * \brief Called just before module is unloaded
+ */
+void UHCI_Cleanup()
+{
+}
+
+/**
+ * \brief Sends a packet to a device endpoint
+ */
+int UHCI_SendPacket(int ControllerId, int Length)
+{
+ //tUHCI_TD *td = UHCI_AllocateTD();
+ return 0;
+}
+
+// === INTERNAL FUNCTIONS ===
+/**
+ * \fn int UHCI_Int_InitHost(tUCHI_Controller *Host)
+ * \brief Initialises a UHCI host controller
+ * \param Host Pointer - Host to initialise
+ */
+int UHCI_Int_InitHost(tUHCI_Controller *Host)
+{
+ ENTER("pHost", Host);
+
+ outw( Host->IOBase + USBCMD, 4 ); // GRESET
+ // TODO: Wait for at least 10ms
+ outw( Host->IOBase + USBCMD, 0 ); // GRESET
+
+ // Allocate Frame List
+ Host->FrameList = (void *) MM_AllocDMA(1, 32, &Host->PhysFrameList); // 1 Page, 32-bit
+ if( !Host->FrameList ) {
+ Log_Warning("UHCI", "Unable to allocate frame list, aborting");
+ LEAVE('i', -1);
+ return -1;
+ }
+ LOG("Allocated frame list 0x%x (0x%x)", Host->FrameList, Host->PhysFrameList);
+ memsetd( Host->FrameList, 1, 1024 ); // Clear List (Disabling all entries)
+
+ //! \todo Properly fill frame list
+
+ // Set frame length to 1 ms
+ outb( Host->IOBase + SOFMOD, 64 );
+
+ // Set Frame List Address
+ outd( Host->IOBase + FLBASEADD, Host->PhysFrameList );
+
+ // Set Frame Number
+ outw( Host->IOBase + FRNUM, 0 );
+
+ // Enable Interrupts
+ //PCI_WriteWord( Host->PciId, 0xC0, 0x2000 );
+
+ LEAVE('i', 0);
+ return 0;
}
-\r
-/**\r
- * \brief Sends a packet to a device endpoint\r
- */\r
-int UHCI_SendPacket(int ControllerId, int Length)\r
-{\r
- //tUHCI_TD *td = UHCI_AllocateTD();\r
- return 0;\r
-}\r
-\r
-// === INTERNAL FUNCTIONS ===\r
-/**\r
- * \fn int UHCI_Int_InitHost(tUCHI_Controller *Host)\r
- * \brief Initialises a UHCI host controller\r
- * \param Host Pointer - Host to initialise\r
- */\r
-int UHCI_Int_InitHost(tUHCI_Controller *Host)\r
-{\r
- ENTER("pHost", Host);\r
- \r
- outw( Host->IOBase + USBCMD, 4 ); // GRESET\r
- // TODO: Wait for at least 10ms\r
- outw( Host->IOBase + USBCMD, 0 ); // GRESET\r
- \r
- // Allocate Frame List\r
- Host->FrameList = (void *) MM_AllocDMA(1, 32, &Host->PhysFrameList); // 1 Page, 32-bit\r
- if( !Host->FrameList ) {\r
- Log_Warning("UHCI", "Unable to allocate frame list, aborting");\r
- LEAVE('i', -1);\r
- return -1;\r
- }\r
- LOG("Allocated frame list 0x%x (0x%x)", Host->FrameList, Host->PhysFrameList);\r
- memsetd( Host->FrameList, 1, 1024 ); // Clear List (Disabling all entries)\r
- \r
- //! \todo Properly fill frame list\r
- \r
- // Set frame length to 1 ms\r
- outb( Host->IOBase + SOFMOD, 64 );\r
- \r
- // Set Frame List Address\r
- outd( Host->IOBase + FLBASEADD, Host->PhysFrameList );\r
- \r
- // Set Frame Number\r
- outw( Host->IOBase + FRNUM, 0 );\r
- \r
- // Enable Interrupts\r
- //PCI_WriteWord( Host->PciId, 0xC0, 0x2000 );\r
- \r
- LEAVE('i', 0);\r
- return 0;\r
-}\r